Tests: Fix some verilog.y parser coverage holes

This commit is contained in:
Wilson Snyder
2024-07-26 07:29:15 -04:00
parent 1600cc01a4
commit 50a5a1ff5b
5 changed files with 13 additions and 5 deletions
+1 -1
View File
@@ -570,7 +570,7 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const VL_MT_STABLE {
}
if (isNull()) {
if (VL_UNCOVERABLE(!isEqZero())) {
out << "-%E-null-not-zero";
out << "-%E-null-not-zero"; // LCOV_EXCL_LINE
} else {
out << " [null]";
}