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Tests: Fix some verilog.y parser coverage holes
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+1
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@@ -570,7 +570,7 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const VL_MT_STABLE {
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}
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if (isNull()) {
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if (VL_UNCOVERABLE(!isEqZero())) {
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out << "-%E-null-not-zero";
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out << "-%E-null-not-zero"; // LCOV_EXCL_LINE
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} else {
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out << " [null]";
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}
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