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Commentary: Changes update

This commit is contained in:
Wilson Snyder 2026-04-23 00:44:50 -04:00
parent 6945f04531
commit 5064a5ee65
55 changed files with 336 additions and 249 deletions
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42
Changes
View File

@ -18,8 +18,23 @@ Verilator 5.047 devel
**Other:**
* Add VPI callback support to `--main` (#7145).
* Add `--func-recursion-depth` option (#7175) (#7179).
* Add `+verilator+solver+file` for debugging constraint solver (#7242).
* Add `--coverage-fsm` for experimental FSM state and arc coverage (#7412). [Yogish Sekhar]
* Add printed summary to verilator_coverage (#7438). [Yogish Sekhar]
* Deprecate `--structs-packed` (#7222).
* Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.]
* Remove multi-threaded FST tracing (#7443). [Geza Lore, Testorrent USA, Inc.]
* Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.]
* Improve error message when variable used as data type (#7318). [Ryszard Rozak, Antmicro Ltd.]
* Improve E_UNSUPPORTED warning messages (#7329). [Eunseo Song]
* Improve NFA-based multi-cycle SVA evaluation engine (#7430). [Yilou Wang]
* Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.]
* Change `--converge-limit` default to 10000 (#7209).
* Support inout inside SV interface (#3466) (#7134). [Nick Brereton]
* Support `##0` cycle delays (#4263) (#7298). [Yilou Wang]
* Support multidimensional arrays of interfaces (#6230) (#7451). [em2machine]
* Support array reduction methods with 'with' clause in constraints (#6455) (#6999). [Rahul Behl]
* Support constraint imperfect distributions (#6811) (#7168). [Yilou Wang]
* Support disable task by name (#6853) (#7136). [Nick Brereton]
@ -39,14 +54,14 @@ Verilator 5.047 devel
* Support modport export/import task prototypes and out-of-block definitions (#7277). [Yilou Wang]
* Support very wide $display arguments (#7280). [Jakub Michalski]
* Support named sequence declarations and instances in assertions (#7283). [Yilou Wang]
* Support `##` delay on implication RHS in SVA properties (#7284). [Yilou Wang]
* Support `##`, `##[*]`, `##[+]`, `##[M:N]` cycle delays in assertions (#7284) (#7312) (#7377). [Yilou Wang]
* Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
* Support property-local variables and sequence match items (#7286). [Yilou Wang]
* Support 'until' property (partial #7290) (#7399). [Ryszard Rozak, Antmicro Ltd.]
* Support 'until' and `until_with` property (#7290 partial) (#7399) (#7436). [Ryszard Rozak, Antmicro Ltd.]
* Support array map() method (#7307) (#7316) (#7344). [Wei-Lun Chiu]
* Support MacOS address sanitizer memory limit (#7308). [Marco Bartoli]
* Support SVA goto repetition `[->N]` in concurrent assertions (#7310). [Yilou Wang]
* Support consecutive repetition `[\*N]` in SVA properties (#7311). [Yilou Wang]
* Support `##[*]`, `##[+]`, `##[M:N]`, `##[M:$]` cycle delays in assertions (#7312) (#7377). [Yilou Wang]
* Support rise/fall delays (#7368). [Artur Bieniek, Antmicro Ltd.]
* Support sequence intersect operator (#7374). [Yilou Wang]
* Support sequence 'throughout' operator (#7378). [Yilou Wang]
@ -55,22 +70,10 @@ Verilator 5.047 devel
* Support nonconsecutive repetition [=N] in sequence expressions (#7397). [Yilou Wang]
* Support per-process RNG for process::srandom() and object seeding (#7408) (#7415) (#7408). [Yilou Wang]
* Support 2**n expressions in constraint randomization (#7422). [Yilou Wang]
* Support `until_with` property (#7290 partial) (#7436). [Ryszard Rozak, Antmicro Ltd.]
* Add VPI callback support to --main (#7145).
* Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
* Add --func-recursion-depth CLI option (#7175) (#7179).
* Add `+verilator+solver+file` (#7242).
* Add MacOS support for address sanitizer memory limit (#7308). [Marco Bartoli]
* Deprecate `--structs-packed` (#7222).
* Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.]
* Improve error message when variable used as data type (#7318). [Ryszard Rozak, Antmicro Ltd.]
* Improve E_UNSUPPORTED warning messages (#7329). [Eunseo Song]
* Improve NFA-based multi-cycle SVA evaluation engine (#7430). [Yilou Wang]
* Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.]
* Change `--converge-limit` default to 10000 (#7209).
* Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.]
* Remove multi-threaded FST tracing (#7443). [Geza Lore, Testorrent USA, Inc.]
* Support IEEE-compliant force/release handling (#7391). [Artur Bieniek, Antmicro Ltd.]
* Support sequence 'within' operator (#7461). [Yilou Wang]
* Optimize trace code for faster compiles on repeated types (#6707) (#6832). [Todd Strader]
* Optimize impure expressions and calls with new V3LiftExpr pass (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
* Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.]
* Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
* Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
@ -87,7 +90,9 @@ Verilator 5.047 devel
* Optimize select patterns in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
* Optimize temporary insertion in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
* Optimize arithmetic right shift (>>>) in DfgBreakCycles (#7447). [Geza Lore, Testorrent USA, Inc.]
* Optimize temporary insertion in DFG (#7459). [Geza Lore, Testorrent USA, Inc.]
* Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
* Fix tracing virtual interface member written from classes (#5044) (#7465). [Nikolay Puzanov]
* Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang]
* Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
* Fix returning wrong type from static function in parameterized class (#5479) (#7387) (#7411) (#7418) (#7445) (#7450). [em2machine]
@ -161,6 +166,7 @@ Verilator 5.047 devel
* Fix inline constraint on array-indexed randomize target (#7431) (#7434). [Yilou Wang]
* Fix modification of members of object with const handle (#7433). [Kamil Danecki, Antmicro Ltd.]
* Fix `dist` under implication in constraints (#7440) (#7442). [Alex Solomatnikov] [Yilou Wang]
* Fix std::randomize `inside` corrupting class-member queue operand (#7449) (#7456). [Yilou Wang]
Verilator 5.046 2026-02-28

1
REUSE.toml
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@ -15,6 +15,7 @@ path = [
".style.yapf",
"CITATION.cff",
"CPPLINT.cfg",
"ci/docker/buildenv/wavetools.conf",
"docs/CONTRIBUTORS",
"docs/spelling.txt",
"docs/verilated.dox",

2
docs/guide/conf.py
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@ -44,7 +44,7 @@ def setup(app):
# -- Project information
project = 'Verilator'
copyright = '2024 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
copyright = '2026 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
author = 'Wilson Snyder'
# The master toctree document.

9
docs/spelling.txt
View File

@ -2,7 +2,6 @@ ABCp
Aadi
Accellera
Aditya
allocator
Affe
Aleksander
Alexandre
@ -363,7 +362,6 @@ Olofsson
Ondrej
Oron
Oyvind
output
PLI
Pakanati
Palaniappan
@ -404,10 +402,8 @@ Ranjan
Rapp
Redhat
Reitan
reentrant
Renga
Requin
reusability
Riaz
Rodas
Rodionov
@ -594,6 +590,7 @@ al
ala
alejandro
algrobman
allocator
andit
ar
architected
@ -815,6 +812,7 @@ fs
fscanf
fseek
fsiegle
fsm
fst
fstrict
ftell
@ -989,6 +987,7 @@ onehot
ooo
oprofile
ortegon
output
oversized
oversubscription
parallelized
@ -1077,12 +1076,14 @@ recrem
recurse
recurses
redeclaring
reentrant
regs
reloop
replaceShiftOp
reproducibility
resetall
respecified
reusability
rodata
rolloverSize
rr

14
nodist/log_changes
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@ -13,14 +13,20 @@ import re
def message_section(msg: str) -> int:
"""Return sorting-section number for given commit message"""
if re.match(r'^Support', msg, flags=re.IGNORECASE):
return 10
if re.match(r'^Add', msg, flags=re.IGNORECASE):
return 10
if re.match(r'^Deprecate', msg, flags=re.IGNORECASE):
return 20
if re.match(r'^Improve', msg, flags=re.IGNORECASE):
if re.match(r'^Remove', msg, flags=re.IGNORECASE):
return 30
if re.match(r'^Fix', msg, flags=re.IGNORECASE):
if re.match(r'^Improve', msg, flags=re.IGNORECASE):
return 40
if re.match(r'^Change', msg, flags=re.IGNORECASE):
return 50
if re.match(r'^Support', msg, flags=re.IGNORECASE):
return 60
if re.match(r'^Fix', msg, flags=re.IGNORECASE):
return 70
if re.match(r'^(Internals|CI|Tests)', msg, flags=re.IGNORECASE):
return -1
if re.match(r'^Bump.* from .* to .*', msg, flags=re.IGNORECASE): # dependabot

13
test_regress/t/t_cover_fsm_basic.out
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@ -11,15 +11,15 @@
typedef enum logic [1:0] {
S_IDLE = 2'd0,
S_RUN = 2'd1,
S_RUN = 2'd1,
S_DONE = 2'd2,
S_ERR = 2'd3
S_ERR = 2'd3
} state_t;
logic rst;
logic start;
integer cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -41,7 +41,8 @@
always_ff @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
end else begin
end
else begin
%000004 case (state)
// [FSM coverage]
%000001 // [fsm_arc t.state::ANY->S_IDLE[reset_include]] [reset arc, excluded from %]
@ -53,7 +54,9 @@
%000000 // [fsm_state t.state::S_ERR] *** UNCOVERED ***
%000000 // [fsm_state t.state::S_IDLE] *** UNCOVERED ***
%000001 // [fsm_state t.state::S_RUN]
S_IDLE: if (start) state <= S_RUN; else state <= S_IDLE;
S_IDLE:
if (start) state <= S_RUN;
else state <= S_IDLE;
S_RUN: state <= S_DONE;
S_DONE: state <= S_DONE;
default: state <= S_ERR;

13
test_regress/t/t_cover_fsm_basic.v
View File

@ -10,15 +10,15 @@ module t (
typedef enum logic [1:0] {
S_IDLE = 2'd0,
S_RUN = 2'd1,
S_RUN = 2'd1,
S_DONE = 2'd2,
S_ERR = 2'd3
S_ERR = 2'd3
} state_t;
logic rst;
logic start;
integer cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -40,9 +40,12 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
end else begin
end
else begin
case (state)
S_IDLE: if (start) state <= S_RUN; else state <= S_IDLE;
S_IDLE:
if (start) state <= S_RUN;
else state <= S_IDLE;
S_RUN: state <= S_DONE;
S_DONE: state <= S_DONE;
default: state <= S_ERR;

11
test_regress/t/t_cover_fsm_beginif.out
View File

@ -7,7 +7,7 @@
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t(
module t (
input logic clk
);
@ -20,7 +20,7 @@
logic rst;
logic sel;
int cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -42,7 +42,8 @@
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
%000003 case (state)
// [FSM coverage]
%000001 // [fsm_arc t.state::ANY->S0[reset_include]] [reset arc, excluded from %]
@ -52,7 +53,9 @@
%000002 // [fsm_state t.state::S0]
%000000 // [fsm_state t.state::S1] *** UNCOVERED ***
%000003 // [fsm_state t.state::S2]
S0: if (sel) state <= S1; else state <= S2;
S0:
if (sel) state <= S1;
else state <= S2;
S1: state <= S0;
default: state <= S0;
endcase

11
test_regress/t/t_cover_fsm_beginif.v
View File

@ -6,7 +6,7 @@
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t(
module t (
input logic clk
);
@ -19,7 +19,7 @@ module t(
logic rst;
logic sel;
int cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -41,9 +41,12 @@ module t(
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
case (state)
S0: if (sel) state <= S1; else state <= S2;
S0:
if (sel) state <= S1;
else state <= S2;
S1: state <= S0;
default: state <= S0;
endcase

4
test_regress/t/t_cover_fsm_enum_bad.out
View File

@ -1,5 +1,5 @@
%Warning-COVERIGN: t/t_cover_fsm_enum_bad.v:27:19: Ignoring unsupported: FSM coverage on enum state transitions that assign a constant not present in the declared enum
27 | S0: state <= 2'd3;
%Warning-COVERIGN: t/t_cover_fsm_enum_bad.v:29:19: Ignoring unsupported: FSM coverage on enum state transitions that assign a constant not present in the declared enum
29 | S0: state <= 2'd3;
| ^~
... For warning description see https://verilator.org/warn/COVERIGN?v=latest
... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.

7
test_regress/t/t_cover_fsm_enum_bad.py
View File

@ -14,11 +14,6 @@ test.scenarios('vlt')
# When an enum-backed FSM assigns a constant that is not one of the declared
# enum items, FSM coverage should warn and skip the unsupported edge rather
# than turning optional coverage into a hard compile failure.
test.lint(verilator_flags2=["--coverage-fsm"], fails=True)
test.file_grep(
test.compile_log_filename,
r'%Warning-COVERIGN: t/t_cover_fsm_enum_bad.v:27:19: Ignoring unsupported: FSM coverage '
r'on enum state transitions that assign a constant not present in the declared enum')
test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename)
test.passes()

6
test_regress/t/t_cover_fsm_enum_bad.v
View File

@ -10,7 +10,8 @@ module t (
);
typedef enum logic [1:0] {
S0, S1
S0,
S1
} state_t;
state_t state;
@ -21,7 +22,8 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
case (state)
/* verilator lint_off ENUMVALUE */
S0: state <= 2'd3;

4
test_regress/t/t_cover_fsm_enumwide_bad.out
View File

@ -1,5 +1,5 @@
%Warning-COVERIGN: t/t_cover_fsm_enumwide_bad.v:25:7: Ignoring unsupported: FSM coverage on enum-typed state variables wider than 32 bits
25 | case (state)
%Warning-COVERIGN: t/t_cover_fsm_enumwide_bad.v:26:7: Ignoring unsupported: FSM coverage on enum-typed state variables wider than 32 bits
26 | case (state)
| ^~~~
... For warning description see https://verilator.org/warn/COVERIGN?v=latest
... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.

7
test_regress/t/t_cover_fsm_enumwide_bad.py
View File

@ -13,11 +13,6 @@ test.scenarios('vlt')
# FSM coverage currently stores recovered enum state values in the detector's
# 32-bit internal representation, so wider enum-backed FSMs are rejected.
test.lint(verilator_flags2=["--coverage-fsm"], fails=True)
test.file_grep(
test.compile_log_filename,
r'%Warning-COVERIGN: t/t_cover_fsm_enumwide_bad.v:25:7: Ignoring unsupported: '
r'FSM coverage on enum-typed state variables wider than 32 bits')
test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename)
test.passes()

3
test_regress/t/t_cover_fsm_enumwide_bad.v
View File

@ -21,7 +21,8 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
case (state)
S0: state <= S1;
default: state <= S0;

13
test_regress/t/t_cover_fsm_flag_off.v
View File

@ -10,15 +10,15 @@ module t (
typedef enum logic [1:0] {
S_IDLE = 2'd0,
S_RUN = 2'd1,
S_RUN = 2'd1,
S_DONE = 2'd2,
S_ERR = 2'd3
S_ERR = 2'd3
} state_t;
logic rst;
logic start;
integer cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -40,9 +40,12 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
end else begin
end
else begin
case (state)
S_IDLE: if (start) state <= S_RUN; else state <= S_IDLE;
S_IDLE:
if (start) state <= S_RUN;
else state <= S_IDLE;
S_RUN: state <= S_DONE;
S_DONE: state <= S_DONE;
default: state <= S_ERR;

5
test_regress/t/t_cover_fsm_forced.out
View File

@ -11,7 +11,7 @@
integer cyc;
logic rst;
logic [1:0] state /*verilator fsm_state*/;
logic [1:0] state /*verilator fsm_state*/;
initial begin
cyc = 0;
@ -30,7 +30,8 @@
always_ff @(posedge clk) begin
if (rst) begin
state <= 2'd0;
end else begin
end
else begin
%000002 case (state)
// [FSM coverage]
%000001 // [fsm_arc t.state::ANY->S0[reset]] [reset arc, excluded from %]

5
test_regress/t/t_cover_fsm_forced.v
View File

@ -10,7 +10,7 @@ module t (
integer cyc;
logic rst;
logic [1:0] state /*verilator fsm_state*/;
logic [1:0] state /*verilator fsm_state*/;
initial begin
cyc = 0;
@ -29,7 +29,8 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= 2'd0;
end else begin
end
else begin
case (state)
2'd0: state <= 2'd1;
2'd1: state <= 2'd2;

5
test_regress/t/t_cover_fsm_negative_extract.out
View File

@ -17,7 +17,7 @@
int cyc;
logic side;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
cyc = 0;
@ -40,7 +40,8 @@
always_ff @(posedge clk) begin
if (cyc == 0) begin
state <= S0;
end else begin
end
else begin
%000002 case (state)
// [FSM coverage]
%000002 // [fsm_arc t.state::S0->S1]

5
test_regress/t/t_cover_fsm_negative_extract.v
View File

@ -16,7 +16,7 @@ module t (
int cyc;
logic side;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
cyc = 0;
@ -39,7 +39,8 @@ module t (
always_ff @(posedge clk) begin
if (cyc == 0) begin
state <= S0;
end else begin
end
else begin
case (state)
S0: state <= S1;
S1: begin

20
test_regress/t/t_cover_fsm_reset.out
View File

@ -16,7 +16,7 @@
%000001 logic rst;
integer cyc;
%000001 state_t state_incl /*verilator fsm_reset_arc*/;
%000001 state_t state_incl /*verilator fsm_reset_arc*/;
%000001 state_t state_excl;
%000001 initial begin
@ -35,28 +35,30 @@
%000006 always_ff @(posedge clk) begin
%000004 if (rst) state_incl <= S0;
%000004 else case (state_incl)
else
%000004 case (state_incl)
// [FSM coverage]
%000001 // [fsm_arc t.state_incl::ANY->S0[reset_include]] [reset arc, excluded from %]
%000001 // [fsm_arc t.state_incl::S0->S1]
%000000 // [fsm_state t.state_incl::S0] *** UNCOVERED ***
%000001 // [fsm_state t.state_incl::S1]
%000001 S0: state_incl <= S1;
%000003 default: state_incl <= S1;
endcase
%000001 S0: state_incl <= S1;
%000003 default: state_incl <= S1;
endcase
end
%000006 always_ff @(posedge clk) begin
%000004 if (rst) state_excl <= S0;
%000004 else case (state_excl)
else
%000004 case (state_excl)
// [FSM coverage]
%000001 // [fsm_arc t.state_excl::ANY->S0[reset]] [reset arc, excluded from %]
%000001 // [fsm_arc t.state_excl::S0->S1]
%000000 // [fsm_state t.state_excl::S0] *** UNCOVERED ***
%000001 // [fsm_state t.state_excl::S1]
%000001 S0: state_excl <= S1;
%000003 default: state_excl <= S1;
endcase
%000001 S0: state_excl <= S1;
%000003 default: state_excl <= S1;
endcase
end
endmodule

20
test_regress/t/t_cover_fsm_reset.v
View File

@ -15,7 +15,7 @@ module t (
logic rst;
integer cyc;
state_t state_incl /*verilator fsm_reset_arc*/;
state_t state_incl /*verilator fsm_reset_arc*/;
state_t state_excl;
initial begin
@ -34,18 +34,20 @@ module t (
always_ff @(posedge clk) begin
if (rst) state_incl <= S0;
else case (state_incl)
S0: state_incl <= S1;
default: state_incl <= S1;
endcase
else
case (state_incl)
S0: state_incl <= S1;
default: state_incl <= S1;
endcase
end
always_ff @(posedge clk) begin
if (rst) state_excl <= S0;
else case (state_excl)
S0: state_excl <= S1;
default: state_excl <= S1;
endcase
else
case (state_excl)
S0: state_excl <= S1;
default: state_excl <= S1;
endcase
end
endmodule

5
test_regress/t/t_cover_fsm_reset_multi.out
View File

@ -17,7 +17,7 @@
logic rst;
integer cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -41,7 +41,8 @@
if (rst) begin
state <= S0;
state <= S1;
end else begin
end
else begin
%000001 case (state)
// [FSM coverage]
%000000 // [fsm_arc t.state::ANY->S0[reset_include]] [reset arc, excluded from %]

5
test_regress/t/t_cover_fsm_reset_multi.v
View File

@ -16,7 +16,7 @@ module t (
logic rst;
integer cyc;
state_t state /*verilator fsm_reset_arc*/;
state_t state /*verilator fsm_reset_arc*/;
initial begin
rst = 1'b1;
@ -40,7 +40,8 @@ module t (
if (rst) begin
state <= S0;
state <= S1;
end else begin
end
else begin
case (state)
S0: state <= S2;
S1: state <= S2;

9
test_regress/t/t_cover_fsm_styles.out
View File

@ -19,7 +19,7 @@
integer cyc;
logic rst;
logic start;
state_t state /*verilator fsm_arc_include_cond*/;
state_t state /*verilator fsm_arc_include_cond*/;
initial begin
rst = 1'b1;
@ -41,7 +41,8 @@
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
%000003 case (state)
// [FSM coverage]
%000001 // [fsm_arc t.state::ANY->S0[reset]] [reset arc, excluded from %]
@ -53,7 +54,9 @@
%000000 // [fsm_state t.state::S1] *** UNCOVERED ***
%000003 // [fsm_state t.state::S2]
%000000 // [fsm_state t.state::S3] *** UNCOVERED ***
S0: if (start) state <= S1; else state <= S2;
S0:
if (start) state <= S1;
else state <= S2;
S1: state <= S3;
default: state <= S0;
endcase

9
test_regress/t/t_cover_fsm_styles.v
View File

@ -18,7 +18,7 @@ module t (
integer cyc;
logic rst;
logic start;
state_t state /*verilator fsm_arc_include_cond*/;
state_t state /*verilator fsm_arc_include_cond*/;
initial begin
rst = 1'b1;
@ -40,9 +40,12 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
case (state)
S0: if (start) state <= S1; else state <= S2;
S0:
if (start) state <= S1;
else state <= S2;
S1: state <= S3;
default: state <= S0;
endcase

2
test_regress/t/t_force_cond.v
View File

@ -5,10 +5,12 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
`define IMPURE_ONE |($random | $random)
// verilog_format: on
module t;
reg [1:0] a = 2;

8
test_regress/t/t_force_nested_struct2.v
View File

@ -10,13 +10,9 @@
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: on
typedef struct packed {
logic [31:0] value;
} Entry;
typedef struct packed {logic [31:0] value;} Entry;
typedef struct packed {
Entry [1:0][1:0] entries;
} DataBlock;
typedef struct packed {Entry [1:0][1:0] entries;} DataBlock;
module sub;
DataBlock data_block;

9
test_regress/t/t_fsm_metacmt_dump.v
View File

@ -14,16 +14,17 @@ module t (
S1 = 1'b1
} state_t;
state_t state_reset /*verilator fsm_reset_arc*/;
state_t state_cond /*verilator fsm_arc_include_cond*/;
logic forced_state /*verilator fsm_state*/;
state_t state_reset /*verilator fsm_reset_arc*/;
state_t state_cond /*verilator fsm_arc_include_cond*/;
logic forced_state /*verilator fsm_state*/;
always_ff @(posedge clk) begin
if (rst) begin
state_reset <= S0;
state_cond <= S0;
forced_state <= 1'b0;
end else begin
end
else begin
state_reset <= S1;
if (state_cond) state_cond <= S0;
else state_cond <= S1;

4
test_regress/t/t_fsmmulti_same_bad.out
View File

@ -1,5 +1,5 @@
%Warning-COVERIGN: t/t_fsmmulti_same_bad.v:30:5: Ignoring unsupported: FSM coverage on multiple supported case statements found in the same always block. Only the first candidate will be instrumented.
30 | case (state)
%Warning-COVERIGN: t/t_fsmmulti_same_bad.v:33:5: Ignoring unsupported: FSM coverage on multiple supported case statements found in the same always block. Only the first candidate will be instrumented.
33 | case (state)
| ^~~~
... For warning description see https://verilator.org/warn/COVERIGN?v=latest
... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.

8
test_regress/t/t_fsmmulti_same_bad.py
View File

@ -15,12 +15,6 @@ test.scenarios('vlt')
# always_ff now warn and keep only the first candidate instrumented. Different-
# state multi-candidate cases still use the existing FSMMULTI warning path; this
# test locks down only the same-state unsupported form.
test.lint(verilator_flags2=["--coverage-fsm"], fails=True)
test.file_grep(
test.compile_log_filename,
r'%Warning-COVERIGN: t/t_fsmmulti_same_bad.v:30:5: Ignoring unsupported: FSM coverage on '
r'multiple supported case statements found in the same always block. Only the first '
r'candidate will be instrumented.')
test.lint(verilator_flags2=["--coverage-fsm"], fails=True, expect_filename=test.golden_filename)
test.passes()

7
test_regress/t/t_fsmmulti_same_bad.v
View File

@ -10,7 +10,9 @@ module t (
);
typedef enum logic [1:0] {
S0, S1, S2
S0,
S1,
S2
} state_t;
state_t state;
@ -21,7 +23,8 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state <= S0;
end else begin
end
else begin
case (state)
S0: state <= S1;
default: ;

4
test_regress/t/t_fsmmulti_warn_bad.out
View File

@ -1,5 +1,5 @@
%Warning-FSMMULTI: t/t_fsmmulti_warn_bad.v:27:5: FSM coverage: multiple enum-typed case statements found in the same always block. Only the first candidate will be instrumented.
27 | case (state_b)
%Warning-FSMMULTI: t/t_fsmmulti_warn_bad.v:29:5: FSM coverage: multiple enum-typed case statements found in the same always block. Only the first candidate will be instrumented.
29 | case (state_b)
| ^~~~
... For warning description see https://verilator.org/warn/FSMMULTI?v=latest
... Use "/* verilator lint_off FSMMULTI */" and lint_on around source to disable this message.

6
test_regress/t/t_fsmmulti_warn_bad.v
View File

@ -9,11 +9,13 @@ module t (
);
typedef enum logic [1:0] {
A0, A1
A0,
A1
} a_state_t;
typedef enum logic [1:0] {
B0, B1
B0,
B1
} b_state_t;
a_state_t state_a;

3
test_regress/t/t_fsmmulti_warn_off.v
View File

@ -26,7 +26,8 @@ module t;
if (rst) begin
a_state <= A0;
b_state <= B0;
end else begin
end
else begin
case (a_state)
A0: a_state <= A1;
A1: a_state <= A2;

6
test_regress/t/t_gate_array_multidim_bad.out
View File

@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_gate_array_multidim_bad.v:12:14: Unsupported: Multidimensional gate instances.
12 | and g [1:0][1:0] (y, a, b);
| ^
%Error-UNSUPPORTED: t/t_gate_array_multidim_bad.v:12:13: Unsupported: Multidimensional gate instances.
12 | and g[1:0][1:0] (y, a, b);
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

2
test_regress/t/t_gate_array_multidim_bad.v
View File

@ -9,5 +9,5 @@
module t;
wire a, b;
wire [1:0][1:0] y;
and g [1:0][1:0] (y, a, b);
and g[1:0][1:0] (y, a, b);
endmodule

7
test_regress/t/t_iface_array_multidim.v
View File

@ -16,7 +16,7 @@ module t;
localparam int A = 2;
localparam int B = 3;
simple_if bus [A-1:0][B-1:0] ();
simple_if bus[A-1:0][B-1:0] ();
genvar gi, gj;
generate
@ -28,7 +28,7 @@ module t;
endgenerate
// Runtime check via a chk array populated by the same genvar generate block.
logic [7:0] chk [A-1:0][B-1:0];
logic [7:0] chk[A-1:0][B-1:0];
generate
for (gi = 0; gi < A; gi++) begin : g_a_chk
for (gj = 0; gj < B; gj++) begin : g_b_chk
@ -42,8 +42,7 @@ module t;
for (int i = 0; i < A; i++) begin
for (int j = 0; j < B; j++) begin
if (chk[i][j] !== 8'(i * B + j + 1)) begin
$write("%%Error: bus[%0d][%0d].data=%0d expected %0d\n",
i, j, chk[i][j], i * B + j + 1);
$write("%%Error: bus[%0d][%0d].data=%0d expected %0d\n", i, j, chk[i][j], i * B + j + 1);
$stop;
end
end

4
test_regress/t/t_iface_array_multidim_3d.v
View File

@ -15,7 +15,7 @@ module t;
localparam int B = 2;
localparam int C = 3;
simple_if bus [A-1:0][B-1:0][C-1:0] ();
simple_if bus[A-1:0][B-1:0][C-1:0] ();
genvar gi, gj, gk;
generate
@ -28,7 +28,7 @@ module t;
end
endgenerate
logic [15:0] chk [A-1:0][B-1:0][C-1:0];
logic [15:0] chk[A-1:0][B-1:0][C-1:0];
generate
for (gi = 0; gi < A; gi++) begin : g_a_chk
for (gj = 0; gj < B; gj++) begin : g_b_chk

8
test_regress/t/t_iface_array_multidim_3d_port.v
View File

@ -11,8 +11,10 @@ interface simple_if;
logic [15:0] data;
endinterface
module sink (simple_if b [1:0][1:0][2:0]);
logic [15:0] chk [1:0][1:0][2:0];
module sink (
simple_if b[1:0][1:0][2:0]
);
logic [15:0] chk[1:0][1:0][2:0];
genvar gi, gj, gk;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -26,7 +28,7 @@ module sink (simple_if b [1:0][1:0][2:0]);
endmodule
module t;
simple_if bus [1:0][1:0][2:0] ();
simple_if bus[1:0][1:0][2:0] ();
sink inst (.b(bus));
genvar gi, gj, gk;

12
test_regress/t/t_iface_array_multidim_hier.v
View File

@ -12,8 +12,10 @@ interface simple_if;
logic [7:0] data;
endinterface
module leaf (simple_if b [1:0][2:0]);
logic [7:0] chk [1:0][2:0];
module leaf (
simple_if b[1:0][2:0]
);
logic [7:0] chk[1:0][2:0];
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -24,12 +26,14 @@ module leaf (simple_if b [1:0][2:0]);
endgenerate
endmodule
module mid (simple_if b [1:0][2:0]);
module mid (
simple_if b[1:0][2:0]
);
leaf leaf_inst (.b(b));
endmodule
module t;
simple_if bus [1:0][2:0] ();
simple_if bus[1:0][2:0] ();
mid mid_inst (.b(bus));
genvar gi, gj;

12
test_regress/t/t_iface_array_multidim_modport.v
View File

@ -14,7 +14,9 @@ interface simple_if;
modport sink(input data);
endinterface
module src (simple_if.source b [1:0][2:0]);
module src (
simple_if.source b[1:0][2:0]
);
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -25,8 +27,10 @@ module src (simple_if.source b [1:0][2:0]);
endgenerate
endmodule
module snk (simple_if.sink b [1:0][2:0]);
logic [7:0] chk [1:0][2:0];
module snk (
simple_if.sink b[1:0][2:0]
);
logic [7:0] chk[1:0][2:0];
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -38,7 +42,7 @@ module snk (simple_if.sink b [1:0][2:0]);
endmodule
module t;
simple_if bus [1:0][2:0] ();
simple_if bus[1:0][2:0] ();
src src_inst (.b(bus));
snk snk_inst (.b(bus));

39
test_regress/t/t_iface_array_multidim_multi_inst.v
View File

@ -10,12 +10,19 @@
// instance finds pinVarp already unlinked and reuses the per-element vars
// cached in m_deModVars.
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
interface simple_if;
logic [7:0] data;
endinterface
module sink (simple_if b [1:0][2:0]);
logic [7:0] chk [1:0][2:0];
module sink (
simple_if b[1:0][2:0]
);
logic [7:0] chk[1:0][2:0];
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -27,8 +34,8 @@ module sink (simple_if b [1:0][2:0]);
endmodule
module t;
simple_if bus1 [1:0][2:0] ();
simple_if bus2 [1:0][2:0] ();
simple_if bus1[1:0][2:0] ();
simple_if bus2[1:0][2:0] ();
sink inst1 (.b(bus1));
sink inst2 (.b(bus2));
@ -46,18 +53,18 @@ module t;
initial begin
#1;
if (inst1.chk[0][0] !== 8'd1) begin $write("%%Error inst1[0][0]=%0d\n", inst1.chk[0][0]); $stop; end
if (inst1.chk[0][1] !== 8'd2) begin $write("%%Error inst1[0][1]=%0d\n", inst1.chk[0][1]); $stop; end
if (inst1.chk[0][2] !== 8'd3) begin $write("%%Error inst1[0][2]=%0d\n", inst1.chk[0][2]); $stop; end
if (inst1.chk[1][0] !== 8'd4) begin $write("%%Error inst1[1][0]=%0d\n", inst1.chk[1][0]); $stop; end
if (inst1.chk[1][1] !== 8'd5) begin $write("%%Error inst1[1][1]=%0d\n", inst1.chk[1][1]); $stop; end
if (inst1.chk[1][2] !== 8'd6) begin $write("%%Error inst1[1][2]=%0d\n", inst1.chk[1][2]); $stop; end
if (inst2.chk[0][0] !== 8'd100) begin $write("%%Error inst2[0][0]=%0d\n", inst2.chk[0][0]); $stop; end
if (inst2.chk[0][1] !== 8'd101) begin $write("%%Error inst2[0][1]=%0d\n", inst2.chk[0][1]); $stop; end
if (inst2.chk[0][2] !== 8'd102) begin $write("%%Error inst2[0][2]=%0d\n", inst2.chk[0][2]); $stop; end
if (inst2.chk[1][0] !== 8'd103) begin $write("%%Error inst2[1][0]=%0d\n", inst2.chk[1][0]); $stop; end
if (inst2.chk[1][1] !== 8'd104) begin $write("%%Error inst2[1][1]=%0d\n", inst2.chk[1][1]); $stop; end
if (inst2.chk[1][2] !== 8'd105) begin $write("%%Error inst2[1][2]=%0d\n", inst2.chk[1][2]); $stop; end
`checkd(inst1.chk[0][0], 8'd1);
`checkd(inst1.chk[0][1], 8'd2);
`checkd(inst1.chk[0][2], 8'd3);
`checkd(inst1.chk[1][0], 8'd4);
`checkd(inst1.chk[1][1], 8'd5);
`checkd(inst1.chk[1][2], 8'd6);
`checkd(inst2.chk[0][0], 8'd100);
`checkd(inst2.chk[0][1], 8'd101);
`checkd(inst2.chk[0][2], 8'd102);
`checkd(inst2.chk[1][0], 8'd103);
`checkd(inst2.chk[1][1], 8'd104);
`checkd(inst2.chk[1][2], 8'd105);
$write("*-* All Finished *-*\n");
$finish;
end

8
test_regress/t/t_iface_array_multidim_nested.v
View File

@ -13,7 +13,7 @@ interface inner_if;
endinterface
interface outer_if;
inner_if inner();
inner_if inner ();
logic [7:0] tag;
endinterface
@ -21,7 +21,7 @@ module t;
localparam int A = 2;
localparam int B = 2;
outer_if oarr [A-1:0][B-1:0] ();
outer_if oarr[A-1:0][B-1:0] ();
genvar gi, gj;
generate
@ -35,8 +35,8 @@ module t;
end
endgenerate
logic [7:0] chk_tag [A-1:0][B-1:0];
logic [7:0] chk_inner [A-1:0][B-1:0];
logic [7:0] chk_tag[A-1:0][B-1:0];
logic [7:0] chk_inner[A-1:0][B-1:0];
generate
for (gi = 0; gi < A; gi++) begin : g_a_chk
for (gj = 0; gj < B; gj++) begin : g_b_chk

12
test_regress/t/t_iface_array_multidim_nested_port.v
View File

@ -13,13 +13,15 @@ interface inner_if;
endinterface
interface outer_if;
inner_if inner();
inner_if inner ();
logic [7:0] tag;
endinterface
module sink (outer_if b [1:0][1:0]);
logic [7:0] chk_tag [1:0][1:0];
logic [7:0] chk_inner [1:0][1:0];
module sink (
outer_if b[1:0][1:0]
);
logic [7:0] chk_tag[1:0][1:0];
logic [7:0] chk_inner[1:0][1:0];
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -32,7 +34,7 @@ module sink (outer_if b [1:0][1:0]);
endmodule
module t;
outer_if oarr [1:0][1:0] ();
outer_if oarr[1:0][1:0] ();
sink inst (.b(oarr));
genvar gi, gj;

8
test_regress/t/t_iface_array_multidim_port.v
View File

@ -13,8 +13,10 @@ interface simple_if;
logic [7:0] data;
endinterface
module sink (simple_if b [1:0][2:0]);
logic [7:0] chk [1:0][2:0];
module sink (
simple_if b[1:0][2:0]
);
logic [7:0] chk[1:0][2:0];
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -26,7 +28,7 @@ module sink (simple_if b [1:0][2:0]);
endmodule
module t;
simple_if bus [1:0][2:0] ();
simple_if bus[1:0][2:0] ();
sink inst (.b(bus));
genvar gi, gj;

23
test_regress/t/t_iface_array_multidim_port_write.v
View File

@ -7,11 +7,18 @@
// Multi-dim iface array port, sink WRITES into the iface signals, top reads.
// Complements t_iface_array_multidim_port (which has sink reading).
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
interface simple_if;
logic [7:0] data;
endinterface
module src (simple_if b [1:0][2:0]);
module src (
simple_if b[1:0][2:0]
);
genvar gi, gj;
generate
for (gi = 0; gi < 2; gi++) begin : g_a
@ -23,17 +30,17 @@ module src (simple_if b [1:0][2:0]);
endmodule
module t;
simple_if bus [1:0][2:0] ();
simple_if bus[1:0][2:0] ();
src inst (.b(bus));
initial begin
#1;
if (bus[0][0].data !== 8'd50) begin $write("%%Error: bus[0][0]=%0d\n", bus[0][0].data); $stop; end
if (bus[0][1].data !== 8'd51) begin $write("%%Error: bus[0][1]=%0d\n", bus[0][1].data); $stop; end
if (bus[0][2].data !== 8'd52) begin $write("%%Error: bus[0][2]=%0d\n", bus[0][2].data); $stop; end
if (bus[1][0].data !== 8'd53) begin $write("%%Error: bus[1][0]=%0d\n", bus[1][0].data); $stop; end
if (bus[1][1].data !== 8'd54) begin $write("%%Error: bus[1][1]=%0d\n", bus[1][1].data); $stop; end
if (bus[1][2].data !== 8'd55) begin $write("%%Error: bus[1][2]=%0d\n", bus[1][2].data); $stop; end
`checkd(bus[0][0].data, 8'd50);
`checkd(bus[0][1].data, 8'd51);
`checkd(bus[0][2].data, 8'd52);
`checkd(bus[1][0].data, 8'd53);
`checkd(bus[1][1].data, 8'd54);
`checkd(bus[1][2].data, 8'd55);
$write("*-* All Finished *-*\n");
$finish;
end

53
test_regress/t/t_iface_array_multidim_ranges.v
View File

@ -9,19 +9,24 @@
// this test exercises the ascending() branch in V3Inst and negative lo() in
// name mangling.
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
interface simple_if;
logic [7:0] data;
endinterface
module t;
// Both dims ascending, zero-based.
simple_if asc [0:1][0:2] ();
simple_if asc[0:1][0:2] ();
// Outer descending, inner ascending (mixed endianness).
simple_if mix [1:0][0:2] ();
simple_if mix[1:0][0:2] ();
// Negative indices: outer descending (1..-1), inner ascending (-2..0).
simple_if neg [1:-1][-2:0] ();
simple_if neg[1:-1][-2:0] ();
initial begin
asc[0][0].data = 8'd10;
@ -51,29 +56,29 @@ module t;
initial begin
#1;
if (asc[0][0].data !== 8'd10) begin $write("%%Error: asc[0][0]=%0d\n", asc[0][0].data); $stop; end
if (asc[0][1].data !== 8'd11) begin $write("%%Error: asc[0][1]=%0d\n", asc[0][1].data); $stop; end
if (asc[0][2].data !== 8'd12) begin $write("%%Error: asc[0][2]=%0d\n", asc[0][2].data); $stop; end
if (asc[1][0].data !== 8'd13) begin $write("%%Error: asc[1][0]=%0d\n", asc[1][0].data); $stop; end
if (asc[1][1].data !== 8'd14) begin $write("%%Error: asc[1][1]=%0d\n", asc[1][1].data); $stop; end
if (asc[1][2].data !== 8'd15) begin $write("%%Error: asc[1][2]=%0d\n", asc[1][2].data); $stop; end
`checkd(asc[0][0].data, 8'd10);
`checkd(asc[0][1].data, 8'd11);
`checkd(asc[0][2].data, 8'd12);
`checkd(asc[1][0].data, 8'd13);
`checkd(asc[1][1].data, 8'd14);
`checkd(asc[1][2].data, 8'd15);
if (mix[0][0].data !== 8'd20) begin $write("%%Error: mix[0][0]=%0d\n", mix[0][0].data); $stop; end
if (mix[0][1].data !== 8'd21) begin $write("%%Error: mix[0][1]=%0d\n", mix[0][1].data); $stop; end
if (mix[0][2].data !== 8'd22) begin $write("%%Error: mix[0][2]=%0d\n", mix[0][2].data); $stop; end
if (mix[1][0].data !== 8'd23) begin $write("%%Error: mix[1][0]=%0d\n", mix[1][0].data); $stop; end
if (mix[1][1].data !== 8'd24) begin $write("%%Error: mix[1][1]=%0d\n", mix[1][1].data); $stop; end
if (mix[1][2].data !== 8'd25) begin $write("%%Error: mix[1][2]=%0d\n", mix[1][2].data); $stop; end
`checkd(mix[0][0].data, 8'd20);
`checkd(mix[0][1].data, 8'd21);
`checkd(mix[0][2].data, 8'd22);
`checkd(mix[1][0].data, 8'd23);
`checkd(mix[1][1].data, 8'd24);
`checkd(mix[1][2].data, 8'd25);
if (neg[-1][-2].data !== 8'd50) begin $write("%%Error: neg[-1][-2]=%0d\n", neg[-1][-2].data); $stop; end
if (neg[-1][-1].data !== 8'd51) begin $write("%%Error: neg[-1][-1]=%0d\n", neg[-1][-1].data); $stop; end
if (neg[-1][0].data !== 8'd52) begin $write("%%Error: neg[-1][0]=%0d\n", neg[-1][0].data); $stop; end
if (neg[0][-2].data !== 8'd53) begin $write("%%Error: neg[0][-2]=%0d\n", neg[0][-2].data); $stop; end
if (neg[0][-1].data !== 8'd54) begin $write("%%Error: neg[0][-1]=%0d\n", neg[0][-1].data); $stop; end
if (neg[0][0].data !== 8'd55) begin $write("%%Error: neg[0][0]=%0d\n", neg[0][0].data); $stop; end
if (neg[1][-2].data !== 8'd56) begin $write("%%Error: neg[1][-2]=%0d\n", neg[1][-2].data); $stop; end
if (neg[1][-1].data !== 8'd57) begin $write("%%Error: neg[1][-1]=%0d\n", neg[1][-1].data); $stop; end
if (neg[1][0].data !== 8'd58) begin $write("%%Error: neg[1][0]=%0d\n", neg[1][0].data); $stop; end
`checkd(neg[-1][-2].data, 8'd50);
`checkd(neg[-1][-1].data, 8'd51);
`checkd(neg[-1][0].data, 8'd52);
`checkd(neg[0][-2].data, 8'd53);
`checkd(neg[0][-1].data, 8'd54);
`checkd(neg[0][0].data, 8'd55);
`checkd(neg[1][-2].data, 8'd56);
`checkd(neg[1][-1].data, 8'd57);
`checkd(neg[1][0].data, 8'd58);
$write("*-* All Finished *-*\n");
$finish;

8
test_regress/t/t_iface_array_multidim_xref.v
View File

@ -8,7 +8,9 @@
// parameterized interface. Exercises IfaceCapture plus the multi-dim
// dotted-access resolver together.
interface bus_if #(parameter int W = 8);
interface bus_if #(
parameter int W = 8
);
logic [W-1:0] data;
endinterface
@ -17,7 +19,7 @@ module holder;
localparam int A = 2;
localparam int B = 3;
bus_if #(.W(8)) bus [A-1:0][B-1:0] ();
bus_if #(.W(8)) bus[A-1:0][B-1:0] ();
genvar gi, gj;
generate
@ -30,7 +32,7 @@ module holder;
endmodule
module t;
holder h();
holder h ();
initial begin
#1;

23
test_regress/t/t_sequence_within.v
View File

@ -16,7 +16,7 @@
// value in a trailing comment for cross-simulator reference.
module t (
input clk
input clk
);
integer cyc = 0;
reg [63:0] crc = '0;
@ -97,20 +97,21 @@ module t (
if (cyc == 0) begin
crc <= 64'h5aef0c8d_d70a4497;
end else if (cyc == 99) begin
end
else if (cyc == 99) begin
`checkh(crc, 64'hc77bb9b3784ea091);
// p1/p2/p5 use |->; the NFA currently fires the pass action on
// vacuous passes too, so counts are inflated vs. Questa. Pre-existing
// engine-wide behavior, not within-specific.
`checkd(count_p1, 89); // Questa: 23
`checkd(count_p2, 89); // Questa: 44
`checkd(count_p3, 26); // Questa: 20
`checkd(count_p4, 24); // Questa: 22
`checkd(count_p5, 89); // Questa: 26
`checkd(count_p6, 21); // Questa: 16
`checkd(count_p7, 15); // Questa: 9
`checkd(count_p8, 15); // Questa: 4
`checkd(count_p9, 17); // Questa: 10
`checkd(count_p1, 89); // Questa: 23
`checkd(count_p2, 89); // Questa: 44
`checkd(count_p3, 26); // Questa: 20
`checkd(count_p4, 24); // Questa: 22
`checkd(count_p5, 89); // Questa: 26
`checkd(count_p6, 21); // Questa: 16
`checkd(count_p7, 15); // Questa: 9
`checkd(count_p8, 15); // Questa: 4
`checkd(count_p9, 17); // Questa: 10
`checkd(count_p10, 24); // Questa: 15
$write("*-* All Finished *-*\n");
$finish;

4
test_regress/t/t_trace_vif_class_clk.v
View File

@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ns
`timescale 1ns / 1ns
`define STRINGIFY(x) `"x`"
interface clk_iface;
@ -24,7 +24,7 @@ class clk_driver;
endclass
module t;
clk_iface ci();
clk_iface ci ();
clk_driver drv;
int x = 0;

6
test_regress/t/t_trace_vif_class_clk_multi.v
View File

@ -4,7 +4,7 @@
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ns
`timescale 1ns / 1ns
`define STRINGIFY(x) `"x`"
interface clk_iface;
@ -24,8 +24,8 @@ class clk_driver;
endclass
module t;
clk_iface ci0();
clk_iface ci1();
clk_iface ci0 ();
clk_iface ci1 ();
clk_driver drv0;
clk_driver drv1;

17
test_regress/t/t_vlcov_fsm_report.out
View File

@ -19,8 +19,8 @@
integer cyc;
%000001 logic rst;
%000001 logic start;
%000003 state_t state_default /*verilator fsm_arc_include_cond*/;
%000001 state_t state_reset_incl /*verilator fsm_reset_arc*/;
%000003 state_t state_default /*verilator fsm_arc_include_cond*/;
%000001 state_t state_reset_incl /*verilator fsm_reset_arc*/;
%000001 state_t state_reset_excl;
%000001 initial begin
@ -45,7 +45,8 @@
%000007 always_ff @(posedge clk) begin
%000005 if (rst) begin
%000002 state_default <= S0;
%000005 end else begin
end
%000005 else begin
%000005 case (state_default)
// [FSM coverage]
%000001 // [fsm_arc t.state_default::ANY->S0[reset]] [reset arc, excluded from %]
@ -54,7 +55,9 @@
%000000 // [fsm_state t.state_default::S1] *** UNCOVERED ***
%000003 // [fsm_state t.state_default::S2]
%000000 // [fsm_state t.state_default::S3] *** UNCOVERED ***
%000003 S0: if (start) state_default <= S1; else state_default <= S2;
%000003 S0:
%000003 if (start) state_default <= S1;
%000003 else state_default <= S2;
%000002 default: state_default <= S0;
endcase
end
@ -65,7 +68,8 @@
%000007 always_ff @(posedge clk) begin
%000005 if (rst) begin
%000002 state_reset_incl <= S0;
%000005 end else begin
end
%000005 else begin
%000005 case (state_reset_incl)
// [FSM coverage]
%000001 // [fsm_arc t.state_reset_incl::ANY->S0[reset_include]] [reset arc, excluded from %]
@ -83,7 +87,8 @@
%000007 always_ff @(posedge clk) begin
%000005 if (rst) begin
%000002 state_reset_excl <= S0;
%000005 end else begin
end
%000005 else begin
%000005 case (state_reset_excl)
// [FSM coverage]
%000001 // [fsm_arc t.state_reset_excl::ANY->S0[reset]] [reset arc, excluded from %]

17
test_regress/t/t_vlcov_fsm_report.v
View File

@ -18,8 +18,8 @@ module t (
integer cyc;
logic rst;
logic start;
state_t state_default /*verilator fsm_arc_include_cond*/;
state_t state_reset_incl /*verilator fsm_reset_arc*/;
state_t state_default /*verilator fsm_arc_include_cond*/;
state_t state_reset_incl /*verilator fsm_reset_arc*/;
state_t state_reset_excl;
initial begin
@ -44,9 +44,12 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state_default <= S0;
end else begin
end
else begin
case (state_default)
S0: if (start) state_default <= S1; else state_default <= S2;
S0:
if (start) state_default <= S1;
else state_default <= S2;
default: state_default <= S0;
endcase
end
@ -57,7 +60,8 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state_reset_incl <= S0;
end else begin
end
else begin
case (state_reset_incl)
S0: state_reset_incl <= S1;
default: state_reset_incl <= S1;
@ -68,7 +72,8 @@ module t (
always_ff @(posedge clk) begin
if (rst) begin
state_reset_excl <= S0;
end else begin
end
else begin
case (state_reset_excl)
S0: state_reset_excl <= S1;
default: state_reset_excl <= S1;

17
test_regress/t/t_vlcov_fsm_report_incl.out
View File

@ -19,8 +19,8 @@
integer cyc;
%000001 logic rst;
%000001 logic start;
%000003 state_t state_default /*verilator fsm_arc_include_cond*/;
%000001 state_t state_reset_incl /*verilator fsm_reset_arc*/;
%000003 state_t state_default /*verilator fsm_arc_include_cond*/;
%000001 state_t state_reset_incl /*verilator fsm_reset_arc*/;
%000001 state_t state_reset_excl;
%000001 initial begin
@ -45,7 +45,8 @@
%000007 always_ff @(posedge clk) begin
%000005 if (rst) begin
%000002 state_default <= S0;
%000005 end else begin
end
%000005 else begin
%000005 case (state_default)
// [FSM coverage]
%000001 // [fsm_arc t.state_default::ANY->S0[reset]]
@ -54,7 +55,9 @@
%000000 // [fsm_state t.state_default::S1] *** UNCOVERED ***
%000003 // [fsm_state t.state_default::S2]
%000000 // [fsm_state t.state_default::S3] *** UNCOVERED ***
%000003 S0: if (start) state_default <= S1; else state_default <= S2;
%000003 S0:
%000003 if (start) state_default <= S1;
%000003 else state_default <= S2;
%000002 default: state_default <= S0;
endcase
end
@ -65,7 +68,8 @@
%000007 always_ff @(posedge clk) begin
%000005 if (rst) begin
%000002 state_reset_incl <= S0;
%000005 end else begin
end
%000005 else begin
%000005 case (state_reset_incl)
// [FSM coverage]
%000001 // [fsm_arc t.state_reset_incl::ANY->S0[reset_include]]
@ -83,7 +87,8 @@
%000007 always_ff @(posedge clk) begin
%000005 if (rst) begin
%000002 state_reset_excl <= S0;
%000005 end else begin
end
%000005 else begin
%000005 case (state_reset_excl)
// [FSM coverage]
%000001 // [fsm_arc t.state_reset_excl::ANY->S0[reset]]