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Support SystemVerilog "cover property" statements.

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This commit is contained in:
Wilson Snyder
2008-08-06 12:52:39 -04:00
parent a76ae67a81
commit 500dc2170f
16 changed files with 396 additions and 94 deletions
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src/V3Width.cpp
+6 -1
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@@ -462,7 +462,11 @@ private:
}
virtual void visit(AstPslClocked* nodep, AstNUser*) {
nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
nodep->sensesp()->iterate(*this);
nodep->sensesp()->iterateAndNext(*this);
if (nodep->disablep()) {
nodep->disablep()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
widthCheckReduce(nodep,"Disable",nodep->disablep(),1,1); // it's like a if() condition.
}
widthCheckReduce(nodep,"Property",nodep->propp(),1,1); // it's like a if() condition.
nodep->width(1,1);
}
@@ -635,6 +639,7 @@ private:
virtual void visit(AstPslCover* nodep, AstNUser*) {
// TOP LEVEL NODE
nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
nodep->stmtsp()->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
widthCheckReduce(nodep,"Property",nodep->propp(),1,1); // it's like a if() condition.
}
virtual void visit(AstPslAssert* nodep, AstNUser*) {