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Convert 'if' tests to assertion macros 

Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
This commit is contained in:
Matthew Ballance 2026-03-07 04:07:50 +00:00
parent 7475dea9f3
commit 4eb676cb49
14 changed files with 123 additions and 152 deletions
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30
test_regress/t/t_covergroup_autobins.v
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@ -4,6 +4,11 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test automatic bin creation when coverpoint has no explicit bins
module t(/*AUTOARG*/
@ -94,26 +99,11 @@ module t(/*AUTOARG*/
$display("CG5 (2 autobins w/ option): %0.1f%%", cg5_inst.get_inst_coverage());
// Validate coverage results
if (cg1_inst.get_inst_coverage() < 30.0 || cg1_inst.get_inst_coverage() > 45.0) begin
$display("FAIL: CG1 coverage out of range");
$stop;
end
if (cg2_inst.get_inst_coverage() < 45.0 || cg2_inst.get_inst_coverage() > 55.0) begin
$display("FAIL: CG2 coverage should be 50%% (2/4 bins with auto_bin_max=4)");
$stop;
end
if (cg3_inst.get_inst_coverage() < 27.0 || cg3_inst.get_inst_coverage() > 30.0) begin
$display("FAIL: CG3 coverage should be ~28.6%% (2/7 valid bins, value 7 ignored)");
$stop;
end
if (cg4_inst.get_inst_coverage() < 95.0) begin
$display("FAIL: CG4 coverage should be 100%%");
$stop;
end
if (cg5_inst.get_inst_coverage() < 99.0) begin
$display("FAIL: CG5 coverage should be 100%% (2/2 bins with auto_bin_max=2)");
$stop;
end
`checkr(cg1_inst.get_inst_coverage(), 37.5);
`checkr(cg2_inst.get_inst_coverage(), 50.0);
`checkr(cg3_inst.get_inst_coverage(), 100.0 * (2.0/7.0));
`checkr(cg4_inst.get_inst_coverage(), 100.0);
`checkr(cg5_inst.get_inst_coverage(), 100.0);
$write("*-* All Finished *-*\n");
$finish;

16
test_regress/t/t_covergroup_bin_counts.v
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@ -6,6 +6,11 @@
// Test viewing individual bin hit counts
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/);
/* verilator lint_off UNSIGNED */
logic [3:0] data;
@ -33,19 +38,10 @@ module t (/*AUTOARG*/);
data = 10; cg_inst.sample(); // high: 1
// Verify coverage is 100% (all 4 bins hit)
check_coverage(100.0, "final");
`checkr(cg_inst.get_inst_coverage(), 100.0);
$write("*-* All Finished *-*\n");
$finish;
end
task check_coverage(real expected, string label);
real cov;
cov = cg_inst.get_inst_coverage();
$display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
if (cov < expected - 0.5 || cov > expected + 0.5) begin
$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
$stop;
end
endtask
endmodule

27
test_regress/t/t_covergroup_coverage_pct.v
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@ -4,6 +4,11 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
@ -29,7 +34,7 @@ module t (/*AUTOARG*/
real cov;
cov = cg_inst.get_inst_coverage();
$display("Coverage after 0 samples: %f", cov);
if (cov != 0.0) $stop;
`checkr(cov, 0.0);
// Cover 1 bin (low) - should be 25%
@(posedge clk);
@ -37,10 +42,7 @@ module t (/*AUTOARG*/
@(posedge clk);
cov = cg_inst.get_inst_coverage();
$display("Coverage after 1/4 bins: %f", cov);
if (cov < 24.9 || cov > 25.1) begin
$display("%%Error: Expected 25%%, got %f", cov);
$stop;
end
`checkr(cov, 25.0);
// Cover 2nd bin (mid1) - should be 50%
@(posedge clk);
@ -48,10 +50,7 @@ module t (/*AUTOARG*/
@(posedge clk);
cov = cg_inst.get_inst_coverage();
$display("Coverage after 2/4 bins: %f", cov);
if (cov < 49.9 || cov > 50.1) begin
$display("%%Error: Expected 50%%, got %f", cov);
$stop;
end
`checkr(cov, 50.0);
// Cover 3rd bin (mid2) - should be 75%
@(posedge clk);
@ -59,10 +58,7 @@ module t (/*AUTOARG*/
@(posedge clk);
cov = cg_inst.get_inst_coverage();
$display("Coverage after 3/4 bins: %f", cov);
if (cov < 74.9 || cov > 75.1) begin
$display("%%Error: Expected 75%%, got %f", cov);
$stop;
end
`checkr(cov, 75.0);
// Cover 4th bin (high) - should be 100%
@(posedge clk);
@ -70,10 +66,7 @@ module t (/*AUTOARG*/
@(posedge clk);
cov = cg_inst.get_inst_coverage();
$display("Coverage after 4/4 bins: %f", cov);
if (cov < 99.9 || cov > 100.1) begin
$display("%%Error: Expected 100%%, got %f", cov);
$stop;
end
`checkr(cov, 100.0);
$write("*-* All Finished *-*\n");
$finish;

25
test_regress/t/t_covergroup_coverage_query.v
View File

@ -6,6 +6,11 @@
// Test querying coverage values via get_inst_coverage
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/);
/* verilator lint_off UNSIGNED */
logic [3:0] data;
@ -24,40 +29,30 @@ module t (/*AUTOARG*/);
cg_inst = new;
// Initially no coverage
check_coverage(0.0, "initial");
`checkr(cg_inst.get_inst_coverage(), 0.0);
// Sample low bin - should be 33.33% (1 of 3 bins)
data = 1;
cg_inst.sample();
check_coverage(33.33, "after low");
`checkr(cg_inst.get_inst_coverage(), 100.0 * (1.0/3.0));
// Sample mid bin - should be 66.67% (2 of 3 bins)
data = 5;
cg_inst.sample();
check_coverage(66.67, "after mid");
`checkr(cg_inst.get_inst_coverage(), 100.0 * (2.0/3.0));
// Sample high bin - should be 100% (3 of 3 bins)
data = 10;
cg_inst.sample();
check_coverage(100.0, "after high");
`checkr(cg_inst.get_inst_coverage(), 100.0);
// Sample again - coverage should still be 100%
data = 2;
cg_inst.sample();
check_coverage(100.0, "after resample");
`checkr(cg_inst.get_inst_coverage(), 100.0);
$write("*-* All Finished *-*\n");
$finish;
end
task check_coverage(real expected, string label);
real cov;
cov = cg_inst.get_inst_coverage();
$display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
// Allow 0.5% tolerance for floating point
if (cov < expected - 0.5 || cov > expected + 0.5) begin
$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
$stop;
end
endtask
endmodule

11
test_regress/t/t_covergroup_cross_3way.v
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@ -4,6 +4,11 @@
// SPDX-FileCopyrightText: 2026 Matthew Ballance
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test 3-way cross coverage
module t;
@ -60,11 +65,7 @@ module t;
// Total = 12 out of 19 = 63.2%
$display("Coverage: %0.1f%%", cg_inst.get_inst_coverage());
if (cg_inst.get_inst_coverage() < 62.0 || cg_inst.get_inst_coverage() > 64.0) begin
$display("%%Error: Expected coverage around 63%%, got %0.1f%%",
cg_inst.get_inst_coverage());
$stop;
end
`checkr(cg_inst.get_inst_coverage(), 1200.0/19.0);
$write("*-* All Finished *-*\n");
$finish;

11
test_regress/t/t_covergroup_cross_4way.v
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@ -4,6 +4,11 @@
// SPDX-FileCopyrightText: 2026 Matthew Ballance
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test 4-way cross coverage
module t;
@ -61,11 +66,7 @@ module t;
// Hit: 2+2+2+2+4 = 12 out of 24 = 50%
$display("Coverage: %0.1f%%", cg_inst.get_inst_coverage());
if (cg_inst.get_inst_coverage() < 49.0 || cg_inst.get_inst_coverage() > 51.0) begin
$display("%%Error: Expected coverage around 50%%, got %0.1f%%",
cg_inst.get_inst_coverage());
$stop;
end
`checkr(cg_inst.get_inst_coverage(), 50.0);
$write("*-* All Finished *-*\n");
$finish;

10
test_regress/t/t_covergroup_cross_large.v
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@ -4,6 +4,11 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test large cross coverage with sparse map implementation
module t(/*AUTOARG*/
@ -67,10 +72,7 @@ module t(/*AUTOARG*/
automatic real inst_cov = cg_inst.get_inst_coverage();
$display("Coverage: %0.1f%%", inst_cov);
if (inst_cov < 1.0 || inst_cov > 100.0) begin
$display("%%Error: Invalid coverage value");
$stop;
end
`checkr(inst_cov, 1100.0/93.0);
$write("*-* All Finished *-*\n");
$finish;

11
test_regress/t/t_covergroup_cross_simple.v
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@ -4,6 +4,11 @@
// SPDX-FileCopyrightText: 2026 Matthew Ballance
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test basic cross coverage with 2-way cross
module t;
@ -52,11 +57,7 @@ module t;
// Total = 9 out of 14 = 64.3%
$display("Coverage: %0.1f%%", cg_inst.get_inst_coverage());
if (cg_inst.get_inst_coverage() < 63.0 || cg_inst.get_inst_coverage() > 65.0) begin
$display("%%Error: Expected coverage around 64%%, got %0.1f%%",
cg_inst.get_inst_coverage());
$stop;
end
`checkr(cg_inst.get_inst_coverage(), 900.0/14.0);
$write("*-* All Finished *-*\n");
$finish;

21
test_regress/t/t_covergroup_dynamic.v
View File

@ -4,6 +4,11 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test dynamic covergroup creation with 'new' operator
module t;
@ -28,23 +33,21 @@ module t;
// Initially no coverage
cov = cg_inst.get_inst_coverage();
$display(" Initial coverage: %f", cov);
if (cov != 0.0) $stop;
`checkr(cov, 0.0);
// Sample low bin
data = 0;
cg_inst.sample();
cov = cg_inst.get_inst_coverage();
$display(" After sampling low: %f", cov);
if (cov < 49.0 || cov > 51.0) $stop; // ~50%
`checkr(cov, 50.0); // ~50%
// Sample high bin
data = 2;
cg_inst.sample();
cov = cg_inst.get_inst_coverage();
$display(" After sampling high: %f", cov);
if (cov < 99.0 || cov > 101.0) $stop; // ~100%
// Test 2: Multiple dynamic instances
`checkr(cov, 100.0); // ~100%
$display("Test 2: Multiple dynamic instances");
begin
cg cg1, cg2, cg3;
@ -66,15 +69,15 @@ module t;
// Check individual coverage
cov = cg1.get_inst_coverage();
$display(" cg1 coverage: %f", cov);
if (cov < 49.0 || cov > 51.0) $stop; // 50%
`checkr(cov, 50.0); // 50%
cov = cg2.get_inst_coverage();
$display(" cg2 coverage: %f", cov);
if (cov < 49.0 || cov > 51.0) $stop; // 50%
`checkr(cov, 50.0); // 50%
cov = cg3.get_inst_coverage();
$display(" cg3 coverage: %f", cov);
if (cov < 49.0 || cov > 51.0) $stop; // 50%
`checkr(cov, 50.0); // 50%
end
// Test 3: Reassignment (old instance should be cleaned up)
@ -84,7 +87,7 @@ module t;
// New instance starts with 0% coverage
cov = cg_inst.get_inst_coverage();
$display(" New instance coverage: %f", cov);
if (cov != 0.0) $stop;
`checkr(cov, 0.0);
$write("*-* All Finished *-*\n");
$finish;

24
test_regress/t/t_covergroup_ignore_bins.v
View File

@ -6,6 +6,11 @@
// Test ignore_bins - excluded from coverage
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/);
/* verilator lint_off UNSIGNED */
logic [3:0] data;
@ -25,39 +30,30 @@ module t (/*AUTOARG*/);
cg_inst = new;
// Initially 0% (0 of 3 regular bins)
check_coverage(0.0, "initial");
`checkr(cg_inst.get_inst_coverage(), 0.0);
// Hit reserved bin - should still be 0%
data = 13;
cg_inst.sample();
check_coverage(0.0, "after reserved");
`checkr(cg_inst.get_inst_coverage(), 0.0);
// Hit low bin - now 33.33% (1 of 3)
data = 1;
cg_inst.sample();
check_coverage(33.33, "after low");
`checkr(cg_inst.get_inst_coverage(), 100.0 * (1.0/3.0));
// Hit another reserved value - still 33.33%
data = 15;
cg_inst.sample();
check_coverage(33.33, "after another reserved");
`checkr(cg_inst.get_inst_coverage(), 100.0 * (1.0/3.0));
// Complete regular bins
data = 5; cg_inst.sample(); // mid
data = 10; cg_inst.sample(); // high
check_coverage(100.0, "complete");
`checkr(cg_inst.get_inst_coverage(), 100.0);
$write("*-* All Finished *-*\n");
$finish;
end
task check_coverage(real expected, string label);
real cov;
cov = cg_inst.get_inst_coverage();
$display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
if (cov < expected - 0.5 || cov > expected + 0.5) begin
$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
$stop;
end
endtask
endmodule

24
test_regress/t/t_covergroup_mixed_bins.v
View File

@ -6,6 +6,11 @@
// Test mixed bin types: single values and ranges
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/);
/* verilator lint_off UNSIGNED */
logic [7:0] opcode;
@ -27,33 +32,24 @@ module t (/*AUTOARG*/);
// Test single value bins
opcode = 8'h00; cg_inst.sample(); // nop
check_coverage(20.0, "after nop");
`checkr(cg_inst.get_inst_coverage(), 20.0);
// Test multi-value list bin
opcode = 8'h02; cg_inst.sample(); // load
check_coverage(40.0, "after load");
`checkr(cg_inst.get_inst_coverage(), 40.0);
opcode = 8'h05; cg_inst.sample(); // store
check_coverage(60.0, "after store");
`checkr(cg_inst.get_inst_coverage(), 60.0);
// Test range bin
opcode = 8'h15; cg_inst.sample(); // arith
check_coverage(80.0, "after arith");
`checkr(cg_inst.get_inst_coverage(), 80.0);
opcode = 8'h80; cg_inst.sample(); // others
check_coverage(100.0, "after others");
`checkr(cg_inst.get_inst_coverage(), 100.0);
$write("*-* All Finished *-*\n");
$finish;
end
task check_coverage(real expected, string label);
real cov;
cov = cg_inst.get_inst_coverage();
$display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
if (cov < expected - 0.5 || cov > expected + 0.5) begin
$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
$stop;
end
endtask
endmodule

30
test_regress/t/t_covergroup_multi_inst.v
View File

@ -6,6 +6,11 @@
// Test multiple covergroup instances with separate tracking
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/);
/* verilator lint_off UNSIGNED */
logic [3:0] data1, data2;
@ -24,37 +29,28 @@ module t (/*AUTOARG*/);
cg_inst2 = new;
// Initially both have 0% coverage
check_coverage(cg_inst1, 0.0, "inst1 initial");
check_coverage(cg_inst2, 0.0, "inst2 initial");
`checkr(cg_inst1.get_inst_coverage(), 0.0);
`checkr(cg_inst2.get_inst_coverage(), 0.0);
// Sample different values in each instance
data1 = 1;
cg_inst1.sample(); // inst1: low covered (50%)
check_coverage(cg_inst1, 50.0, "inst1 after low");
check_coverage(cg_inst2, 0.0, "inst2 still empty");
`checkr(cg_inst1.get_inst_coverage(), 50.0);
`checkr(cg_inst2.get_inst_coverage(), 0.0);
data1 = 10;
cg_inst2.sample(); // inst2: high covered (50%)
check_coverage(cg_inst1, 50.0, "inst1 still 50%");
check_coverage(cg_inst2, 50.0, "inst2 after high");
`checkr(cg_inst1.get_inst_coverage(), 50.0);
`checkr(cg_inst2.get_inst_coverage(), 50.0);
// Complete coverage in inst1
data1 = 8;
cg_inst1.sample(); // inst1: both covered (100%)
check_coverage(cg_inst1, 100.0, "inst1 complete");
check_coverage(cg_inst2, 50.0, "inst2 still 50%");
`checkr(cg_inst1.get_inst_coverage(), 100.0);
`checkr(cg_inst2.get_inst_coverage(), 50.0);
$write("*-* All Finished *-*\n");
$finish;
end
task check_coverage(cg inst, real expected, string label);
real cov;
cov = inst.get_inst_coverage();
$display("Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
if (cov < expected - 0.5 || cov > expected + 0.5) begin
$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
$stop;
end
endtask
endmodule

20
test_regress/t/t_covergroup_realistic.v
View File

@ -6,6 +6,11 @@
// Realistic example: Bus transaction coverage
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/);
/* verilator lint_off UNSIGNED */
logic [31:0] addr;
@ -44,27 +49,18 @@ module t (/*AUTOARG*/);
addr = 32'h0000_1100; burst_type = 2'b01; cg_inst.sample();
// After boot
check_coverage(50.0, "after boot");
`checkr(cg_inst.get_inst_coverage(), 50.0);
// DRAM access with wrap burst
addr = 32'h4000_0000; burst_type = 2'b10; cg_inst.sample();
check_coverage(75.0, "after dram access");
`checkr(cg_inst.get_inst_coverage(), 75.0);
// Peripheral access completes all addr bins
addr = 32'h8000_0100; burst_type = 2'b11; cg_inst.sample();
check_coverage(100.0, "complete");
`checkr(cg_inst.get_inst_coverage(), 100.0);
$write("*-* All Finished *-*\n");
$finish;
end
task check_coverage(real expected, string label);
real cov;
cov = cg_inst.get_inst_coverage();
$display("Bus Coverage %s: %0.2f%% (expected ~%0.2f%%)", label, cov, expected);
if (cov < expected - 1.0 || cov > expected + 1.0) begin
$error("Coverage mismatch: got %0.2f%%, expected ~%0.2f%%", cov, expected);
$stop;
end
endtask
endmodule

15
test_regress/t/t_covergroup_static_coverage.v
View File

@ -8,6 +8,11 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;
covergroup cg;
@ -31,7 +36,7 @@ module t;
// Initially, no bins covered - should be 0%
type_cov = cg::get_coverage();
$display("Initial type coverage: %f", type_cov);
if (type_cov != 0.0) $stop;
`checkr(type_cov, 0.0);
// Sample cg1 with low bin
data = 0;
@ -39,7 +44,7 @@ module t;
type_cov = cg::get_coverage();
$display("After cg1.sample(low): %f", type_cov);
// 1 bin covered out of 3 = 33.33%
if (type_cov < 33.0 || type_cov > 34.0) $stop;
`checkr(type_cov, 100.0/3.0);
// Sample cg2 with mid bin
data = 2;
@ -47,7 +52,7 @@ module t;
type_cov = cg::get_coverage();
$display("After cg2.sample(mid): %f", type_cov);
// 2 bins covered out of 3 = 66.67%
if (type_cov < 66.0 || type_cov > 67.0) $stop;
`checkr(type_cov, 200.0/3.0);
// Sample cg3 with high bin
data = 4;
@ -55,14 +60,14 @@ module t;
type_cov = cg::get_coverage();
$display("After cg3.sample(high): %f", type_cov);
// 3 bins covered out of 3 = 100%
if (type_cov < 99.9 || type_cov > 100.1) $stop;
`checkr(type_cov, 100.0);
// Sample cg1 again with same bin - should not change coverage
data = 1;
cg1.sample();
type_cov = cg::get_coverage();
$display("After cg1.sample(low again): %f", type_cov);
if (type_cov < 99.9 || type_cov > 100.1) $stop;
`checkr(type_cov, 100.0);
$write("*-* All Finished *-*\n");
$finish;