Tests: Add t_uvm_all

test_regress/t/t_dist_copyright.pl

@@ -41,6 +41,7 @@ our @Exempt_Files_List = qw(
     test_regress/t/t_fuzz_eof_bad.v
     test_regress/t/t_incr_void.v
     test_regress/t/t_timing_trace_fst.pl
+    test_regress/t/t_uvm_pkg_all.vh
     test_regress/t/t_wrapper_context.pl
     test_regress/t/t_wrapper_context_fst.pl
     test_regress/t/t_wrapper_context_seq.pl

test_regress/t/t_uvm_all.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    v_flags2 => ["-Wno-PKGNODECL -Wno-UNPACKED -Wno-RANDC -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT",
+                 "--error-limit 200 --debug-exit-uvm"],
+    );
+
+#execute(
+#    check_finished => 1,
+#    );
+
+ok(1);
+1;

test_regress/t/t_uvm_all.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`include "t_uvm_pkg_all.vh"
+
+module t(/*AUTOARG*/);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule