Add missing SPDX-FileCopyrightText headers to covergroup test files
All new covergroup test files were missing the canonical SPDX-FileCopyrightText line required by t_dist_copyright. Add it above the existing SPDX-License-Identifier line in each file. Also canonicalize t_covergroup_with_sample_args_too_many_bad.py to use SPDX form instead of prose copyright comment. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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#include "verilated.h"
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// DESCRIPTION: Verilator: Test automatic sampling with clocking events
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// Tests --no-timing (default) mode; see t_covergroup_auto_sample_timing for --timing variant.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Covergroup with INTERNAL clock using explicit sampling
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Covergroup with clocking event using MODULE INPUT clock
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test small cross coverage with inline implementation
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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#include "verilated.h"
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// DESCRIPTION: Verilator: Verilog Test module - Edge case: empty covergroup
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Empty covergroup (no coverpoints)
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// DESCRIPTION: Verilator: Verilog Test module - Edge case: multiple instances
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Multiple instances of same covergroup type sampling the same coverpoint
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// DESCRIPTION: Verilator: Verilog Test module - Edge case: negative value ranges
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Bins with negative value ranges
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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// Known limitation: multi-value (3+) transition bins generate incomplete case
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// statements; complex transitions are not fully supported.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// DESCRIPTION: Verilator: Test transition bins - array bins
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// Transition array bins are supported.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Known limitation: multi-value transition bins with restart semantics generate
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// incomplete case statements; complex transitions are not fully supported.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// DESCRIPTION: Verilator: Test transition bins - simple two-value transitions
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2025 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off COVERIGN */
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