Fix trace hierarchicalName runtime errors (#5668) (#6076).

Changes

@@ -28,6 +28,7 @@ Verilator 5.037 devel
 * Improve hierarchical scheduling visualization in V3ExecGraph (#6009). [Bartłomiej Chmiel, Antmicro Ltd.]
 * Improve DPI temporary 'for' loop performance (#6079). [Bartłomiej Chmiel, Antmicro Ltd.]
 * Fix --x-initial and --x-assign random stability (#2662) (#5958) (#6018) (#6025) (#6075). [Todd Strader]
+* Fix trace hierarchicalName runtime errors (#5668) (#6076). [Paul Swirhun]
 * Fix filename backslash escapes in C code (#5947).
 * Fix C++ widths in V3Expand (#5953) (#5975). [Geza Lore]
 * Fix dependencies from different hierarchical schedules (#5954). [Bartłomiej Chmiel, Antmicro Ltd.]

include/verilated_fst_c.cpp

@@ -140,7 +140,6 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elemen
 // TODO: should return std::optional<fstScopeType>, but I can't have C++17
 static std::pair<bool, fstScopeType> toFstScopeType(VerilatedTracePrefixType type) {
     switch (type) {
-    case VerilatedTracePrefixType::ROOTIO_MODULE: return {true, FST_ST_VCD_MODULE};
     case VerilatedTracePrefixType::SCOPE_MODULE: return {true, FST_ST_VCD_MODULE};
     case VerilatedTracePrefixType::SCOPE_INTERFACE: return {true, FST_ST_VCD_INTERFACE};
     case VerilatedTracePrefixType::STRUCT_PACKED:
@@ -152,19 +151,23 @@ static std::pair<bool, fstScopeType> toFstScopeType(VerilatedTracePrefixType typ
 
 void VerilatedFst::pushPrefix(const std::string& name, VerilatedTracePrefixType type) {
     assert(!m_prefixStack.empty());  // Constructor makes an empty entry
-    std::string pname = name;
+    // An empty name means this is the root of a model created with
-    // An empty name means this is the root of a model created with name()=="".  The
+    // name()=="".  The tools get upset if we try to pass this as empty, so
-    // tools get upset if we try to pass this as empty, so we put the signals under a
+    // we put the signals under a new $rootio scope, but the signals
-    // new scope, but the signals further down will be peers, not children (as usual
+    // further down will be peers, not children (as usual for name()!="").
-    // for name()!="")
+    const std::string prevPrefix = m_prefixStack.back().first;
-    // Terminate earlier $root?
+    if (name == "$rootio" && !prevPrefix.empty()) {
-    if (m_prefixStack.back().second == VerilatedTracePrefixType::ROOTIO_MODULE) popPrefix();
+        // Upper has name, we can suppress inserting $rootio, but still push so popPrefix works
-    if (pname.empty()) {  // Start new temporary root
+        m_prefixStack.emplace_back(prevPrefix, VerilatedTracePrefixType::ROOTIO_WRAPPER);
-        pname = "$rootio";  // VCD names are not backslash escaped
+        return;
-        m_prefixStack.emplace_back("", VerilatedTracePrefixType::ROOTIO_WRAPPER);
+    } else if (name.empty()) {
-        type = VerilatedTracePrefixType::ROOTIO_MODULE;
+        m_prefixStack.emplace_back(prevPrefix, VerilatedTracePrefixType::ROOTIO_WRAPPER);
+        return;
     }
-    const std::string newPrefix = m_prefixStack.back().first + pname;
+
+    // This code assumes a signal at a given prefix level is declared before
+    // any pushPrefix are done at that same level.
+    const std::string newPrefix = prevPrefix + name;
     const auto pair = toFstScopeType(type);
     const bool properScope = pair.first;
     const fstScopeType scopeType = pair.second;

include/verilated_saif_c.cpp

@@ -475,18 +475,25 @@ void VerilatedSaif::printIndent() {
 }
 
 void VerilatedSaif::pushPrefix(const std::string& name, VerilatedTracePrefixType type) {
-    std::string pname = name;
+    assert(!m_prefixStack.empty());  // Constructor makes an empty entry
-
+    // An empty name means this is the root of a model created with
-    if (m_prefixStack.back().second == VerilatedTracePrefixType::ROOTIO_MODULE) popPrefix();
+    // name()=="".  The tools get upset if we try to pass this as empty, so
-    if (pname.empty()) {
+    // we put the signals under a new $rootio scope, but the signals
-        pname = "$rootio";
+    // further down will be peers, not children (as usual for name()!="").
-        type = VerilatedTracePrefixType::ROOTIO_MODULE;
+    const std::string prevPrefix = m_prefixStack.back().first;
+    if (name == "$rootio" && !prevPrefix.empty()) {
+        // Upper has name, we can suppress inserting $rootio, but still push so popPrefix works
+        m_prefixStack.emplace_back(prevPrefix, VerilatedTracePrefixType::ROOTIO_WRAPPER);
+        return;
+    } else if (name.empty()) {
+        m_prefixStack.emplace_back(prevPrefix, VerilatedTracePrefixType::ROOTIO_WRAPPER);
+        return;
     }
 
     if (type != VerilatedTracePrefixType::ARRAY_UNPACKED
         && type != VerilatedTracePrefixType::ARRAY_PACKED) {
 
-        std::string scopePath = m_prefixStack.back().first + pname;
+        std::string scopePath = prevPrefix + name;
         std::string scopeName = lastWord(scopePath);
 
         auto newScope = std::make_unique<VerilatedSaifActivityScope>(
@@ -502,23 +509,22 @@ void VerilatedSaif::pushPrefix(const std::string& name, VerilatedTracePrefixType
         m_currentScope = newScopePtr;
     }
 
-    std::string newPrefix = m_prefixStack.back().first + pname;
+    const std::string newPrefix = prevPrefix + name;
-    if (type != VerilatedTracePrefixType::ARRAY_UNPACKED
+    bool properScope = (type != VerilatedTracePrefixType::ARRAY_UNPACKED
-        && type != VerilatedTracePrefixType::ARRAY_PACKED) {
+                        && type != VerilatedTracePrefixType::ARRAY_PACKED
-        newPrefix += ' ';
+                        && type != VerilatedTracePrefixType::ROOTIO_WRAPPER);
-    }
+    m_prefixStack.emplace_back(newPrefix + (properScope ? " " : ""), type);
-
-    m_prefixStack.emplace_back(newPrefix, type);
 }
 
 void VerilatedSaif::popPrefix() {
     if (m_prefixStack.back().second != VerilatedTracePrefixType::ARRAY_UNPACKED
         && m_prefixStack.back().second != VerilatedTracePrefixType::ARRAY_PACKED
-        && m_currentScope != nullptr) {
+        && m_prefixStack.back().second != VerilatedTracePrefixType::ROOTIO_WRAPPER
+        && m_currentScope) {
         m_currentScope = m_currentScope->parentScope();
     }
-
     m_prefixStack.pop_back();
+    assert(!m_prefixStack.empty());  // Always one left, the constructor's initial one
 }
 
 void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name,

include/verilated_trace.h

@@ -53,8 +53,7 @@ enum class VerilatedTracePrefixType : uint8_t {
     // Note: Entries must match VTracePrefixType (by name, not necessarily by value)
     ARRAY_PACKED,
     ARRAY_UNPACKED,
-    ROOTIO_MODULE,  // $rootio, used when name()=="", other modules become peers
+    ROOTIO_WRAPPER,  // $rootio suppressed due to name()!=""
-    ROOTIO_WRAPPER,  // "Above" ROOTIO_MODULE
     SCOPE_MODULE,
     SCOPE_INTERFACE,
     STRUCT_PACKED,

include/verilated_vcd_c.cpp

@@ -323,43 +323,46 @@ void VerilatedVcd::printIndent(int level_change) {
 
 void VerilatedVcd::pushPrefix(const std::string& name, VerilatedTracePrefixType type) {
     assert(!m_prefixStack.empty());  // Constructor makes an empty entry
-    std::string pname = name;
+    // An empty name means this is the root of a model created with
-    // An empty name means this is the root of a model created with name()=="".  The
+    // name()=="".  The tools get upset if we try to pass this as empty, so
-    // tools get upset if we try to pass this as empty, so we put the signals under a
+    // we put the signals under a new $rootio scope, but the signals
-    // new scope, but the signals further down will be peers, not children (as usual
+    // further down will be peers, not children (as usual for name()!="").
-    // for name()!="")
+    const std::string prevPrefix = m_prefixStack.back().first;
-    // Terminate earlier $root?
+    if (name == "$rootio" && !prevPrefix.empty()) {
-    if (m_prefixStack.back().second == VerilatedTracePrefixType::ROOTIO_MODULE) popPrefix();
+        // Upper has name, we can suppress inserting $rootio, but still push so popPrefix works
-    if (pname.empty()) {  // Start new temporary root
+        m_prefixStack.emplace_back(prevPrefix, VerilatedTracePrefixType::ROOTIO_WRAPPER);
-        pname = "$rootio";  // VCD names are not backslash escaped
+        return;
-        m_prefixStack.emplace_back("", VerilatedTracePrefixType::ROOTIO_WRAPPER);
+    } else if (name.empty()) {
-        type = VerilatedTracePrefixType::ROOTIO_MODULE;
+        m_prefixStack.emplace_back(prevPrefix, VerilatedTracePrefixType::ROOTIO_WRAPPER);
+        return;
     }
-    std::string newPrefix = m_prefixStack.back().first + pname;
+
+    const std::string newPrefix = prevPrefix + name;
+    bool properScope = false;
     switch (type) {
-    case VerilatedTracePrefixType::ROOTIO_MODULE:
     case VerilatedTracePrefixType::SCOPE_MODULE:
     case VerilatedTracePrefixType::SCOPE_INTERFACE:
     case VerilatedTracePrefixType::STRUCT_PACKED:
     case VerilatedTracePrefixType::STRUCT_UNPACKED:
     case VerilatedTracePrefixType::UNION_PACKED: {
+        properScope = true;
+        break;
+    }
+    default: break;
+    }
+    if (properScope) {
         printIndent(1);
         printStr("$scope module ");
         const std::string n = lastWord(newPrefix);
         printStr(n.c_str());
         printStr(" $end\n");
-        newPrefix += ' ';
-        break;
     }
-    default: break;
+    m_prefixStack.emplace_back(newPrefix + (properScope ? " " : ""), type);
-    }
-    m_prefixStack.emplace_back(newPrefix, type);
 }
 
 void VerilatedVcd::popPrefix() {
     assert(!m_prefixStack.empty());
     switch (m_prefixStack.back().second) {
-    case VerilatedTracePrefixType::ROOTIO_MODULE:
     case VerilatedTracePrefixType::SCOPE_MODULE:
     case VerilatedTracePrefixType::SCOPE_INTERFACE:
     case VerilatedTracePrefixType::STRUCT_PACKED:

src/V3TraceDecl.cpp

@@ -120,14 +120,11 @@ class TraceDeclVisitor final : public VNVisitor {
     // - A sub scope (stored as the cell corresponding to the sub scope)
     // Note: members are non-const to allow copy during sorting
     class TraceEntry final {
-        // AstVarScope under scope being traced
+        AstVarScope* m_vscp = nullptr;  // AstVarScope under scope being traced
-        AstVarScope* m_vscp{nullptr};
+        AstCell* m_cellp = nullptr;  // Sub scope (as AstCell) under scope being traced
-        // Sub scope (as AstCell) under scope being traced
+        std::string m_path;  // Path to enclosing module in original hierarchy
-        AstCell* m_cellp{nullptr};
+        std::string m_name;  // Name of signal/subscope
-        // Path to enclosing module in original hierarchy (non-trivail due to inlining)
+        bool m_rootio = false;  // Is part of $rootio, if model at runtime uses name()=""
-        std::string m_path;
-        // Name of signal/subscope
-        std::string m_name;
 
         void init(const std::string& name) {
             // Compute path in hierarchy and item name
@@ -147,12 +144,21 @@ class TraceDeclVisitor final : public VNVisitor {
             : m_cellp{cellp} {
             init(cellp->name());
         }
-
+        int operatorCompare(const TraceEntry& b) const {
+            if (rootio() && !b.rootio()) return true;
+            if (!rootio() && b.rootio()) return false;
+            if (const int cmp = path().compare(b.path())) return cmp < 0;
+            if (const int cmp = fileline().operatorCompare(b.fileline())) return cmp < 0;
+            return name() < b.name();
+        }
         AstVarScope* vscp() const { return m_vscp; }
         AstCell* cellp() const { return m_cellp; }
         const std::string& path() const { return m_path; }
+        void path(const std::string& path) { m_path = path; }
         const std::string& name() const { return m_name; }
         FileLine& fileline() const { return m_vscp ? *m_vscp->fileline() : *m_cellp->fileline(); }
+        bool rootio() const { return m_rootio; }
+        void rootio(bool flag) { m_rootio = flag; }
     };
     std::vector<TraceEntry> m_entries;  // Trace entries under current scope
     AstVarScope* m_traVscp = nullptr;  // Current AstVarScope we are constructing AstTraceDecls for
@@ -367,23 +373,29 @@ class TraceDeclVisitor final : public VNVisitor {
         }
 
         if (!m_entries.empty()) {
-            // Sort trace entries, first by enclosing instance (necessary for
+            if (nodep->name() == "TOP") {
-            // single traversal of hierarchy during initialization), then by
+                UINFO(9, " Add $rootio " << nodep);
-            // source location, then by name.
+                for (TraceEntry& entry : m_entries) {
-            std::stable_sort(m_entries.begin(), m_entries.end(),
+                    if (entry.path() == "" && entry.vscp()) entry.rootio(true);
-                             [](const TraceEntry& a, const TraceEntry& b) {
+                }
-                                 if (const int cmp = a.path().compare(b.path())) return cmp < 0;
+            }
-                                 if (const int cmp = a.fileline().operatorCompare(b.fileline()))
+
-                                     return cmp < 0;
+            // Sort trace entries, first by if a $root io, then by enclosing instance
-                                 return a.name() < b.name();
+            // (necessary for single traversal of hierarchy during initialization), then
-                             });
+            // by source location, then by name.
+            std::stable_sort(
+                m_entries.begin(), m_entries.end(),
+                [](const TraceEntry& a, const TraceEntry& b) { return a.operatorCompare(b); });
 
             // Build trace initialization functions for this AstScope
             FileLine* const flp = nodep->fileline();
             PathAdjustor pathAdjustor{flp, [&](AstNodeStmt* stmtp) { addToSubFunc(stmtp); }};
             for (const TraceEntry& entry : m_entries) {
                 // Adjust name prefix based on path in hierarchy
-                pathAdjustor.adjust(entry.path());
+                UINFO(9, "path='" << entry.path() << "' name='" << entry.name() << "' "
+                                  << (entry.cellp() ? static_cast<AstNode*>(entry.cellp())
+                                                    : static_cast<AstNode*>(entry.vscp())));
+                pathAdjustor.adjust(entry.rootio() ? "$rootio" : entry.path());
 
                 m_traName = entry.name();
 

test_regress/t/t_clocker.out

@@ -1,14 +1,13 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module top $end
-  $scope module $unit $end
-   $var wire 32 + ID_MSB [31:0] $end
-  $upscope $end
   $var wire 1 # clk $end
   $var wire 1 $ res $end
   $var wire 8 % res8 [7:0] $end
   $var wire 16 & res16 [15:0] $end
+  $scope module $unit $end
+   $var wire 32 + ID_MSB [31:0] $end
+  $upscope $end
   $scope module t $end
    $var wire 1 # clk $end
    $var wire 1 $ res $end

test_regress/t/t_cover_line_trace.out

@@ -1,6 +1,7 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
+  $var wire 1 4! clk $end
   $scope module t $end
    $var wire 1 4! clk $end
    $var wire 1 A toggle $end
@@ -175,7 +176,6 @@ $timescale 1ps $end
     $var wire 32 '! vlCoverageLineTrace_t_cover_line__276_block [31:0] $end
    $upscope $end
   $upscope $end
-  $var wire 1 4! clk $end
   $scope module my_pkg $end
    $var wire 32 + x [31:0] $end
    $var wire 32 , vlCoverageLineTrace_t_cover_line__300_block [31:0] $end

test_regress/t/t_cover_trace_always.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module t $end
   $var wire 1 $ p $end
   $var wire 1 % q $end

test_regress/t/t_flag_csplit_groups.py

@@ -124,7 +124,7 @@ test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_clas
 test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2")
 
 # Check combine count
-test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (231 if test.vltmt else 211))
+test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (234 if test.vltmt else 214))
 test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_FAST + (\d+)', 2)
 test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_SLOW + (\d+)', 2)
 

test_regress/t/t_hier_trace_noinl.out

@@ -1,6 +1,8 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
+  $var wire 1 # clk $end
+  $var wire 1 $ reset_l $end
   $scope module t $end
    $var wire 1 # clk $end
    $var wire 1 $ reset_l $end
@@ -13,10 +15,10 @@ $timescale 1ps $end
     $var wire 1 $ reset_l $end
    $upscope $end
   $upscope $end
-  $var wire 1 # clk $end
-  $var wire 1 $ reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top $end
+  $var wire 1 & clk $end
+  $var wire 1 ' reset_l $end
   $scope module sub_top $end
    $var wire 1 & clk $end
    $var wire 1 ' reset_l $end
@@ -53,10 +55,10 @@ $timescale 1ps $end
     $var wire 1 ' reset_l $end
    $upscope $end
   $upscope $end
-  $var wire 1 & clk $end
-  $var wire 1 ' reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top $end
+  $var wire 1 ) clk $end
+  $var wire 1 * reset_l $end
   $scope module sub_top $end
    $var wire 1 ) clk $end
    $var wire 1 * reset_l $end
@@ -93,136 +95,134 @@ $timescale 1ps $end
     $var wire 1 * reset_l $end
    $upscope $end
   $upscope $end
-  $var wire 1 ) clk $end
-  $var wire 1 * reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u0 $end
+  $var wire 1 , clk $end
+  $var wire 1 - reset_l $end
   $scope module detail_code $end
    $var wire 1 , clk $end
    $var wire 1 - reset_l $end
   $upscope $end
-  $var wire 1 , clk $end
-  $var wire 1 - reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u1 $end
+  $var wire 1 / clk $end
+  $var wire 1 0 reset_l $end
   $scope module detail_code $end
    $var wire 1 / clk $end
    $var wire 1 0 reset_l $end
   $upscope $end
-  $var wire 1 / clk $end
-  $var wire 1 0 reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u2 $end
+  $var wire 1 2 clk $end
+  $var wire 1 3 reset_l $end
   $scope module detail_code $end
    $var wire 1 2 clk $end
    $var wire 1 3 reset_l $end
   $upscope $end
-  $var wire 1 2 clk $end
-  $var wire 1 3 reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u3 $end
+  $var wire 1 5 clk $end
+  $var wire 1 6 reset_l $end
   $scope module detail_code $end
    $var wire 1 5 clk $end
    $var wire 1 6 reset_l $end
   $upscope $end
-  $var wire 1 5 clk $end
-  $var wire 1 6 reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u4 $end
+  $var wire 1 8 clk $end
+  $var wire 1 9 reset_l $end
   $scope module detail_code $end
    $var wire 1 8 clk $end
    $var wire 1 9 reset_l $end
   $upscope $end
-  $var wire 1 8 clk $end
-  $var wire 1 9 reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u5 $end
+  $var wire 1 ; clk $end
+  $var wire 1 < reset_l $end
   $scope module detail_code $end
    $var wire 1 ; clk $end
    $var wire 1 < reset_l $end
   $upscope $end
-  $var wire 1 ; clk $end
-  $var wire 1 < reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u6 $end
+  $var wire 1 > clk $end
+  $var wire 1 ? reset_l $end
   $scope module detail_code $end
    $var wire 1 > clk $end
    $var wire 1 ? reset_l $end
   $upscope $end
-  $var wire 1 > clk $end
-  $var wire 1 ? reset_l $end
  $upscope $end
  $scope module top.t.u0_sub_top.sub_top.u7 $end
+  $var wire 1 A clk $end
+  $var wire 1 B reset_l $end
   $scope module detail_code $end
    $var wire 1 A clk $end
    $var wire 1 B reset_l $end
   $upscope $end
-  $var wire 1 A clk $end
-  $var wire 1 B reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u0 $end
+  $var wire 1 D clk $end
+  $var wire 1 E reset_l $end
   $scope module detail_code $end
    $var wire 1 D clk $end
    $var wire 1 E reset_l $end
   $upscope $end
-  $var wire 1 D clk $end
-  $var wire 1 E reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u1 $end
+  $var wire 1 G clk $end
+  $var wire 1 H reset_l $end
   $scope module detail_code $end
    $var wire 1 G clk $end
    $var wire 1 H reset_l $end
   $upscope $end
-  $var wire 1 G clk $end
-  $var wire 1 H reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u2 $end
+  $var wire 1 J clk $end
+  $var wire 1 K reset_l $end
   $scope module detail_code $end
    $var wire 1 J clk $end
    $var wire 1 K reset_l $end
   $upscope $end
-  $var wire 1 J clk $end
-  $var wire 1 K reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u3 $end
+  $var wire 1 M clk $end
+  $var wire 1 N reset_l $end
   $scope module detail_code $end
    $var wire 1 M clk $end
    $var wire 1 N reset_l $end
   $upscope $end
-  $var wire 1 M clk $end
-  $var wire 1 N reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u4 $end
+  $var wire 1 P clk $end
+  $var wire 1 Q reset_l $end
   $scope module detail_code $end
    $var wire 1 P clk $end
    $var wire 1 Q reset_l $end
   $upscope $end
-  $var wire 1 P clk $end
-  $var wire 1 Q reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u5 $end
+  $var wire 1 S clk $end
+  $var wire 1 T reset_l $end
   $scope module detail_code $end
    $var wire 1 S clk $end
    $var wire 1 T reset_l $end
   $upscope $end
-  $var wire 1 S clk $end
-  $var wire 1 T reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u6 $end
+  $var wire 1 V clk $end
+  $var wire 1 W reset_l $end
   $scope module detail_code $end
    $var wire 1 V clk $end
    $var wire 1 W reset_l $end
   $upscope $end
-  $var wire 1 V clk $end
-  $var wire 1 W reset_l $end
  $upscope $end
  $scope module top.t.u1_sub_top.sub_top.u7 $end
+  $var wire 1 Y clk $end
+  $var wire 1 Z reset_l $end
   $scope module detail_code $end
    $var wire 1 Y clk $end
    $var wire 1 Z reset_l $end
   $upscope $end
-  $var wire 1 Y clk $end
-  $var wire 1 Z reset_l $end
  $upscope $end
 $enddefinitions $end
 

test_regress/t/t_interface_ref_trace_noinl.out

@@ -1,7 +1,7 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module top $end
+  $var wire 1 0 clk $end
   $scope module t $end
    $var wire 1 0 clk $end
    $var wire 32 # cyc [31:0] $end
@@ -294,7 +294,6 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
   $upscope $end
-  $var wire 1 0 clk $end
  $upscope $end
 $enddefinitions $end
 

test_regress/t/t_timing_osc.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1fs $end
- $scope module $rootio $end
- $upscope $end
  $scope module tb_osc $end
   $var wire 1 # dco_out $end
   $scope module dco $end

test_regress/t/t_timing_trace.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module t $end
   $var wire 32 * CLK_PERIOD [31:0] $end
   $var wire 32 + CLK_HALF_PERIOD [31:0] $end

test_regress/t/t_timing_trace_fst.out

@@ -1,5 +1,5 @@
 $date
-	Fri May  2 07:32:42 2025
+	Tue Jun 10 19:01:39 2025
 
 $end
 $version
@@ -8,8 +8,6 @@ $end
 $timescale
 	1ps
 $end
-$scope module $rootio $end
-$upscope $end
 $scope module t $end
 $var parameter 32 ! CLK_PERIOD [31:0] $end
 $var parameter 32 " CLK_HALF_PERIOD [31:0] $end

test_regress/t/t_timing_trace_saif.out

@@ -6,8 +6,6 @@
 (DIVIDER / )
 (TIMESCALE 1ps)
 (DURATION 100)
- (INSTANCE $rootio
- )
  (INSTANCE t
   (NET
    (CLK_PERIOD\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))

test_regress/t/t_trace_binary.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module t $end
   $var wire 32 # sig [31:0] $end
  $upscope $end

test_regress/t/t_trace_class.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module $unit::Cls__P0__Vclpkg $end
   $var wire 32 # PARAM [31:0] $end
  $upscope $end

test_regress/t/t_trace_complex.out

@@ -1,38 +1,38 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
+  $var wire 1 = clk $end
   $scope module $unit $end
    $var wire 1 # global_bit $end
   $upscope $end
-  $var wire 1 4 clk $end
   $scope module t $end
-   $var wire 1 4 clk $end
+   $var wire 1 = clk $end
-   $var wire 32 5 cyc [31:0] $end
+   $var wire 32 $ cyc [31:0] $end
-   $var wire 2 ) v_strp [1:0] $end
+   $var wire 2 % v_strp [1:0] $end
-   $var wire 4 * v_strp_strp [3:0] $end
+   $var wire 4 & v_strp_strp [3:0] $end
-   $var wire 2 - v_unip_strp [1:0] $end
+   $var wire 2 ' v_unip_strp [1:0] $end
-   $var wire 2 . v_arrp [2:1] $end
+   $var wire 2 ( v_arrp [2:1] $end
-   $var wire 4 $ v_arrp_arrp [3:0] $end
+   $var wire 4 ) v_arrp_arrp [3:0] $end
-   $var wire 4 / v_arrp_strp [3:0] $end
+   $var wire 4 * v_arrp_strp [3:0] $end
    $var wire 1 > v_arru[1] $end
    $var wire 1 ? v_arru[2] $end
    $var wire 1 @ v_arru_arru[3][1] $end
    $var wire 1 A v_arru_arru[3][2] $end
    $var wire 1 B v_arru_arru[4][1] $end
    $var wire 1 C v_arru_arru[4][2] $end
-   $var wire 2 6 v_arru_arrp[3] [2:1] $end
+   $var wire 2 + v_arru_arrp[3] [2:1] $end
-   $var wire 2 7 v_arru_arrp[4] [2:1] $end
+   $var wire 2 , v_arru_arrp[4] [2:1] $end
-   $var wire 2 8 v_arru_strp[3] [1:0] $end
+   $var wire 2 - v_arru_strp[3] [1:0] $end
-   $var wire 2 9 v_arru_strp[4] [1:0] $end
+   $var wire 2 . v_arru_strp[4] [1:0] $end
-   $var real 64 % v_real $end
+   $var real 64 / v_real $end
-   $var real 64 : v_arr_real[0] $end
+   $var real 64 1 v_arr_real[0] $end
-   $var real 64 < v_arr_real[1] $end
+   $var real 64 3 v_arr_real[1] $end
    $var wire 64 D v_chandle [63:0] $end
-   $var wire 64 0 v_str32x2 [63:0] $end
+   $var wire 64 5 v_str32x2 [63:0] $end
-   $var wire 32 + v_enumed [31:0] $end
+   $var wire 32 7 v_enumed [31:0] $end
-   $var wire 32 , v_enumed2 [31:0] $end
+   $var wire 32 8 v_enumed2 [31:0] $end
-   $var wire 3 2 v_enumb [2:0] $end
+   $var wire 3 9 v_enumb [2:0] $end
-   $var wire 6 3 v_enumb2_str [5:0] $end
+   $var wire 6 : v_enumb2_str [5:0] $end
    $var wire 8 F unpacked_array[-2] [7:0] $end
    $var wire 8 G unpacked_array[-1] [7:0] $end
    $var wire 8 H unpacked_array[0] [7:0] $end
@@ -47,9 +47,9 @@ $timescale 1ps $end
     $var wire 32 L PARAM [31:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 ' b [31:0] $end
+    $var wire 32 ; b [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 ( a [31:0] $end
+     $var wire 32 < a [31:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -59,28 +59,28 @@ $enddefinitions $end
 
 #0
 1#
-b0000 $
+b00000000000000000000000000000000 $
-r0 %
+b00 %
-b00000000000000000000000000000000 '
+b0000 &
-b00000000000000000000000000000000 (
+b00 '
-b00 )
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000000 +
+b00 +
-b00000000000000000000000000000000 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0 /
-b0000000000000000000000000000000000000000000000000000000011111111 0
+r0 1
-b000 2
+r0 3
-b000000 3
+b0000000000000000000000000000000000000000000000000000000011111111 5
-04
+b00000000000000000000000000000000 7
-b00000000000000000000000000000000 5
+b00000000000000000000000000000000 8
-b00 6
+b000 9
-b00 7
+b000000 :
-b00 8
+b00000000000000000000000000000000 ;
-b00 9
+b00000000000000000000000000000000 <
-r0 :
+0=
-r0 <
 0>
 0?
 0@
@@ -96,139 +96,139 @@ b00000000000000000000000000000100 J
 b00000000000000000000000000000010 K
 b00000000000000000000000000000011 L
 #10
-b1111 $
+b00000000000000000000000000000001 $
-r0.1 %
+b11 %
-b00000000000000000000000000000101 '
+b1111 &
-b00000000000000000000000000000101 (
+b11 '
-b11 )
+b11 (
+b1111 )
 b1111 *
-b00000000000000000000000000000001 +
+b11 +
-b00000000000000000000000000000010 ,
+b11 ,
 b11 -
 b11 .
-b1111 /
+r0.1 /
-b0000000000000000000000000000000100000000000000000000000011111110 0
+r0.2 1
-b111 2
+r0.3 3
-14
+b0000000000000000000000000000000100000000000000000000000011111110 5
-b00000000000000000000000000000001 5
+b00000000000000000000000000000001 7
-b11 6
+b00000000000000000000000000000010 8
-b11 7
+b111 9
-b11 8
+b00000000000000000000000000000101 ;
-b11 9
+b00000000000000000000000000000101 <
-r0.2 :
+1=
-r0.3 <
 #15
-04
+0=
 #20
-b0000 $
+b00000000000000000000000000000010 $
-r0.2 %
+b00 %
-b00 )
+b0000 &
+b00 '
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000010 +
+b00 +
-b00000000000000000000000000000100 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0.2 /
-b0000000000000000000000000000001000000000000000000000000011111101 0
+r0.4 1
-b110 2
+r0.6 3
-b111111 3
+b0000000000000000000000000000001000000000000000000000000011111101 5
-14
+b00000000000000000000000000000010 7
-b00000000000000000000000000000010 5
+b00000000000000000000000000000100 8
-b00 6
+b110 9
-b00 7
+b111111 :
-b00 8
+1=
-b00 9
-r0.4 :
-r0.6 <
 #25
-04
+0=
 #30
-b1111 $
+b00000000000000000000000000000011 $
-r0.3 %
+b11 %
-b11 )
+b1111 &
+b11 '
+b11 (
+b1111 )
 b1111 *
-b00000000000000000000000000000011 +
+b11 +
-b00000000000000000000000000000110 ,
+b11 ,
 b11 -
 b11 .
-b1111 /
+r0.3 /
-b0000000000000000000000000000001100000000000000000000000011111100 0
+r0.6000000000000001 1
-b101 2
+r0.8999999999999999 3
-b110110 3
+b0000000000000000000000000000001100000000000000000000000011111100 5
-14
+b00000000000000000000000000000011 7
-b00000000000000000000000000000011 5
+b00000000000000000000000000000110 8
-b11 6
+b101 9
-b11 7
+b110110 :
-b11 8
+1=
-b11 9
-r0.6000000000000001 :
-r0.8999999999999999 <
 #35
-04
+0=
 #40
-b0000 $
+b00000000000000000000000000000100 $
-r0.4 %
+b00 %
-b00 )
+b0000 &
+b00 '
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000100 +
+b00 +
-b00000000000000000000000000001000 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0.4 /
-b0000000000000000000000000000010000000000000000000000000011111011 0
+r0.8 1
-b100 2
+r1.2 3
-b101101 3
+b0000000000000000000000000000010000000000000000000000000011111011 5
-14
+b00000000000000000000000000000100 7
-b00000000000000000000000000000100 5
+b00000000000000000000000000001000 8
-b00 6
+b100 9
-b00 7
+b101101 :
-b00 8
+1=
-b00 9
-r0.8 :
-r1.2 <
 #45
-04
+0=
 #50
-b1111 $
+b00000000000000000000000000000101 $
-r0.5 %
+b11 %
-b11 )
+b1111 &
+b11 '
+b11 (
+b1111 )
 b1111 *
-b00000000000000000000000000000101 +
+b11 +
-b00000000000000000000000000001010 ,
+b11 ,
 b11 -
 b11 .
-b1111 /
+r0.5 /
-b0000000000000000000000000000010100000000000000000000000011111010 0
+r1 1
-b011 2
+r1.5 3
-b100100 3
+b0000000000000000000000000000010100000000000000000000000011111010 5
-14
+b00000000000000000000000000000101 7
-b00000000000000000000000000000101 5
+b00000000000000000000000000001010 8
-b11 6
+b011 9
-b11 7
+b100100 :
-b11 8
+1=
-b11 9
-r1 :
-r1.5 <
 #55
-04
+0=
 #60
-b0000 $
+b00000000000000000000000000000110 $
-r0.6 %
+b00 %
-b00 )
+b0000 &
+b00 '
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000110 +
+b00 +
-b00000000000000000000000000001100 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0.6 /
-b0000000000000000000000000000011000000000000000000000000011111001 0
+r1.2 1
-b010 2
+r1.8 3
-b011011 3
+b0000000000000000000000000000011000000000000000000000000011111001 5
-14
+b00000000000000000000000000000110 7
-b00000000000000000000000000000110 5
+b00000000000000000000000000001100 8
-b00 6
+b010 9
-b00 7
+b011011 :
-b00 8
+1=
-b00 9
-r1.2 :
-r1.8 <

test_regress/t/t_trace_complex_fst.out

@@ -1,5 +1,5 @@
 $date
-	Thu Jan 25 08:01:43 2024
+	Tue Jun 10 19:02:36 2025
 
 $end
 $version
@@ -11,12 +11,12 @@ $end
 $scope module top $end
 $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
 $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
+$var wire 1 ! clk $end
 $scope module $unit $end
-$var bit 1 ! global_bit $end
+$var bit 1 " global_bit $end
 $upscope $end
-$var wire 1 " clk $end
 $scope module t $end
-$var wire 1 " clk $end
+$var wire 1 ! clk $end
 $var integer 32 # cyc [31:0] $end
 $var bit 2 $ v_strp [1:0] $end
 $var bit 4 % v_strp_strp [3:0] $end
@@ -105,11 +105,11 @@ b00 &
 b0000 %
 b00 $
 b00000000000000000000000000000000 #
-0"
+1"
-1!
+0!
 $end
 #10
-1"
+1!
 b00000000000000000000000000000001 #
 b11 $
 b1111 %
@@ -131,9 +131,9 @@ b111 ;
 b00000000000000000000000000000101 D
 b00000000000000000000000000000101 E
 #15
-0"
+0!
 #20
-1"
+1!
 b110 ;
 b00000000000000000000000000000100 :
 b00000000000000000000000000000010 9
@@ -154,9 +154,9 @@ b00 $
 b00000000000000000000000000000010 #
 b111111 <
 #25
-0"
+0!
 #30
-1"
+1!
 b110110 <
 b00000000000000000000000000000011 #
 b11 $
@@ -177,9 +177,9 @@ b00000000000000000000000000000011 9
 b00000000000000000000000000000110 :
 b101 ;
 #35
-0"
+0!
 #40
-1"
+1!
 b100 ;
 b00000000000000000000000000001000 :
 b00000000000000000000000000000100 9
@@ -200,9 +200,9 @@ b00 $
 b00000000000000000000000000000100 #
 b101101 <
 #45
-0"
+0!
 #50
-1"
+1!
 b100100 <
 b00000000000000000000000000000101 #
 b11 $
@@ -223,9 +223,9 @@ b00000000000000000000000000000101 9
 b00000000000000000000000000001010 :
 b011 ;
 #55
-0"
+0!
 #60
-1"
+1!
 b010 ;
 b00000000000000000000000000001100 :
 b00000000000000000000000000000110 9

test_regress/t/t_trace_complex_params.out

@@ -1,38 +1,38 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
+  $var wire 1 = clk $end
   $scope module $unit $end
    $var wire 1 # global_bit $end
   $upscope $end
-  $var wire 1 4 clk $end
   $scope module t $end
-   $var wire 1 4 clk $end
+   $var wire 1 = clk $end
-   $var wire 32 5 cyc [31:0] $end
+   $var wire 32 $ cyc [31:0] $end
-   $var wire 2 ) v_strp [1:0] $end
+   $var wire 2 % v_strp [1:0] $end
-   $var wire 4 * v_strp_strp [3:0] $end
+   $var wire 4 & v_strp_strp [3:0] $end
-   $var wire 2 - v_unip_strp [1:0] $end
+   $var wire 2 ' v_unip_strp [1:0] $end
-   $var wire 2 . v_arrp [2:1] $end
+   $var wire 2 ( v_arrp [2:1] $end
-   $var wire 4 $ v_arrp_arrp [3:0] $end
+   $var wire 4 ) v_arrp_arrp [3:0] $end
-   $var wire 4 / v_arrp_strp [3:0] $end
+   $var wire 4 * v_arrp_strp [3:0] $end
    $var wire 1 > v_arru[1] $end
    $var wire 1 ? v_arru[2] $end
    $var wire 1 @ v_arru_arru[3][1] $end
    $var wire 1 A v_arru_arru[3][2] $end
    $var wire 1 B v_arru_arru[4][1] $end
    $var wire 1 C v_arru_arru[4][2] $end
-   $var wire 2 6 v_arru_arrp[3] [2:1] $end
+   $var wire 2 + v_arru_arrp[3] [2:1] $end
-   $var wire 2 7 v_arru_arrp[4] [2:1] $end
+   $var wire 2 , v_arru_arrp[4] [2:1] $end
-   $var wire 2 8 v_arru_strp[3] [1:0] $end
+   $var wire 2 - v_arru_strp[3] [1:0] $end
-   $var wire 2 9 v_arru_strp[4] [1:0] $end
+   $var wire 2 . v_arru_strp[4] [1:0] $end
-   $var real 64 % v_real $end
+   $var real 64 / v_real $end
-   $var real 64 : v_arr_real[0] $end
+   $var real 64 1 v_arr_real[0] $end
-   $var real 64 < v_arr_real[1] $end
+   $var real 64 3 v_arr_real[1] $end
    $var wire 64 D v_chandle [63:0] $end
-   $var wire 64 0 v_str32x2 [63:0] $end
+   $var wire 64 5 v_str32x2 [63:0] $end
-   $var wire 32 + v_enumed [31:0] $end
+   $var wire 32 7 v_enumed [31:0] $end
-   $var wire 32 , v_enumed2 [31:0] $end
+   $var wire 32 8 v_enumed2 [31:0] $end
-   $var wire 3 2 v_enumb [2:0] $end
+   $var wire 3 9 v_enumb [2:0] $end
-   $var wire 6 3 v_enumb2_str [5:0] $end
+   $var wire 6 : v_enumb2_str [5:0] $end
    $var wire 8 F unpacked_array[-2] [7:0] $end
    $var wire 8 G unpacked_array[-1] [7:0] $end
    $var wire 8 H unpacked_array[0] [7:0] $end
@@ -47,9 +47,9 @@ $timescale 1ps $end
     $var wire 32 L PARAM [31:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 ' b [31:0] $end
+    $var wire 32 ; b [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 ( a [31:0] $end
+     $var wire 32 < a [31:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -59,28 +59,28 @@ $enddefinitions $end
 
 #0
 1#
-b0000 $
+b00000000000000000000000000000000 $
-r0 %
+b00 %
-b00000000000000000000000000000000 '
+b0000 &
-b00000000000000000000000000000000 (
+b00 '
-b00 )
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000000 +
+b00 +
-b00000000000000000000000000000000 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0 /
-b0000000000000000000000000000000000000000000000000000000011111111 0
+r0 1
-b000 2
+r0 3
-b000000 3
+b0000000000000000000000000000000000000000000000000000000011111111 5
-04
+b00000000000000000000000000000000 7
-b00000000000000000000000000000000 5
+b00000000000000000000000000000000 8
-b00 6
+b000 9
-b00 7
+b000000 :
-b00 8
+b00000000000000000000000000000000 ;
-b00 9
+b00000000000000000000000000000000 <
-r0 :
+0=
-r0 <
 0>
 0?
 0@
@@ -96,139 +96,139 @@ b00000000000000000000000000000100 J
 b00000000000000000000000000000010 K
 b00000000000000000000000000000011 L
 #10
-b1111 $
+b00000000000000000000000000000001 $
-r0.1 %
+b11 %
-b00000000000000000000000000000101 '
+b1111 &
-b00000000000000000000000000000101 (
+b11 '
-b11 )
+b11 (
+b1111 )
 b1111 *
-b00000000000000000000000000000001 +
+b11 +
-b00000000000000000000000000000010 ,
+b11 ,
 b11 -
 b11 .
-b1111 /
+r0.1 /
-b0000000000000000000000000000000100000000000000000000000011111110 0
+r0.2 1
-b111 2
+r0.3 3
-14
+b0000000000000000000000000000000100000000000000000000000011111110 5
-b00000000000000000000000000000001 5
+b00000000000000000000000000000001 7
-b11 6
+b00000000000000000000000000000010 8
-b11 7
+b111 9
-b11 8
+b00000000000000000000000000000101 ;
-b11 9
+b00000000000000000000000000000101 <
-r0.2 :
+1=
-r0.3 <
 #15
-04
+0=
 #20
-b0000 $
+b00000000000000000000000000000010 $
-r0.2 %
+b00 %
-b00 )
+b0000 &
+b00 '
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000010 +
+b00 +
-b00000000000000000000000000000100 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0.2 /
-b0000000000000000000000000000001000000000000000000000000011111101 0
+r0.4 1
-b110 2
+r0.6 3
-b111111 3
+b0000000000000000000000000000001000000000000000000000000011111101 5
-14
+b00000000000000000000000000000010 7
-b00000000000000000000000000000010 5
+b00000000000000000000000000000100 8
-b00 6
+b110 9
-b00 7
+b111111 :
-b00 8
+1=
-b00 9
-r0.4 :
-r0.6 <
 #25
-04
+0=
 #30
-b1111 $
+b00000000000000000000000000000011 $
-r0.3 %
+b11 %
-b11 )
+b1111 &
+b11 '
+b11 (
+b1111 )
 b1111 *
-b00000000000000000000000000000011 +
+b11 +
-b00000000000000000000000000000110 ,
+b11 ,
 b11 -
 b11 .
-b1111 /
+r0.3 /
-b0000000000000000000000000000001100000000000000000000000011111100 0
+r0.6000000000000001 1
-b101 2
+r0.8999999999999999 3
-b110110 3
+b0000000000000000000000000000001100000000000000000000000011111100 5
-14
+b00000000000000000000000000000011 7
-b00000000000000000000000000000011 5
+b00000000000000000000000000000110 8
-b11 6
+b101 9
-b11 7
+b110110 :
-b11 8
+1=
-b11 9
-r0.6000000000000001 :
-r0.8999999999999999 <
 #35
-04
+0=
 #40
-b0000 $
+b00000000000000000000000000000100 $
-r0.4 %
+b00 %
-b00 )
+b0000 &
+b00 '
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000100 +
+b00 +
-b00000000000000000000000000001000 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0.4 /
-b0000000000000000000000000000010000000000000000000000000011111011 0
+r0.8 1
-b100 2
+r1.2 3
-b101101 3
+b0000000000000000000000000000010000000000000000000000000011111011 5
-14
+b00000000000000000000000000000100 7
-b00000000000000000000000000000100 5
+b00000000000000000000000000001000 8
-b00 6
+b100 9
-b00 7
+b101101 :
-b00 8
+1=
-b00 9
-r0.8 :
-r1.2 <
 #45
-04
+0=
 #50
-b1111 $
+b00000000000000000000000000000101 $
-r0.5 %
+b11 %
-b11 )
+b1111 &
+b11 '
+b11 (
+b1111 )
 b1111 *
-b00000000000000000000000000000101 +
+b11 +
-b00000000000000000000000000001010 ,
+b11 ,
 b11 -
 b11 .
-b1111 /
+r0.5 /
-b0000000000000000000000000000010100000000000000000000000011111010 0
+r1 1
-b011 2
+r1.5 3
-b100100 3
+b0000000000000000000000000000010100000000000000000000000011111010 5
-14
+b00000000000000000000000000000101 7
-b00000000000000000000000000000101 5
+b00000000000000000000000000001010 8
-b11 6
+b011 9
-b11 7
+b100100 :
-b11 8
+1=
-b11 9
-r1 :
-r1.5 <
 #55
-04
+0=
 #60
-b0000 $
+b00000000000000000000000000000110 $
-r0.6 %
+b00 %
-b00 )
+b0000 &
+b00 '
+b00 (
+b0000 )
 b0000 *
-b00000000000000000000000000000110 +
+b00 +
-b00000000000000000000000000001100 ,
+b00 ,
 b00 -
 b00 .
-b0000 /
+r0.6 /
-b0000000000000000000000000000011000000000000000000000000011111001 0
+r1.2 1
-b010 2
+r1.8 3
-b011011 3
+b0000000000000000000000000000011000000000000000000000000011111001 5
-14
+b00000000000000000000000000000110 7
-b00000000000000000000000000000110 5
+b00000000000000000000000000001100 8
-b00 6
+b010 9
-b00 7
+b011011 :
-b00 8
+1=
-b00 9
-r1.2 :
-r1.8 <

test_regress/t/t_trace_complex_params_fst.out

@@ -1,5 +1,5 @@
 $date
-	Thu Jan 25 08:07:29 2024
+	Tue Jun 10 19:02:39 2025
 
 $end
 $version
@@ -11,12 +11,12 @@ $end
 $scope module top $end
 $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
 $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
+$var wire 1 ! clk $end
 $scope module $unit $end
-$var bit 1 ! global_bit $end
+$var bit 1 " global_bit $end
 $upscope $end
-$var wire 1 " clk $end
 $scope module t $end
-$var wire 1 " clk $end
+$var wire 1 ! clk $end
 $var integer 32 # cyc [31:0] $end
 $var bit 2 $ v_strp [1:0] $end
 $var bit 4 % v_strp_strp [3:0] $end
@@ -105,11 +105,11 @@ b00 &
 b0000 %
 b00 $
 b00000000000000000000000000000000 #
-0"
+1"
-1!
+0!
 $end
 #10
-1"
+1!
 b00000000000000000000000000000001 #
 b11 $
 b1111 %
@@ -131,9 +131,9 @@ b111 ;
 b00000000000000000000000000000101 D
 b00000000000000000000000000000101 E
 #15
-0"
+0!
 #20
-1"
+1!
 b110 ;
 b00000000000000000000000000000100 :
 b00000000000000000000000000000010 9
@@ -154,9 +154,9 @@ b00 $
 b00000000000000000000000000000010 #
 b111111 <
 #25
-0"
+0!
 #30
-1"
+1!
 b110110 <
 b00000000000000000000000000000011 #
 b11 $
@@ -177,9 +177,9 @@ b00000000000000000000000000000011 9
 b00000000000000000000000000000110 :
 b101 ;
 #35
-0"
+0!
 #40
-1"
+1!
 b100 ;
 b00000000000000000000000000001000 :
 b00000000000000000000000000000100 9
@@ -200,9 +200,9 @@ b00 $
 b00000000000000000000000000000100 #
 b101101 <
 #45
-0"
+0!
 #50
-1"
+1!
 b100100 <
 b00000000000000000000000000000101 #
 b11 $
@@ -223,9 +223,9 @@ b00000000000000000000000000000101 9
 b00000000000000000000000000001010 :
 b011 ;
 #55
-0"
+0!
 #60
-1"
+1!
 b010 ;
 b00000000000000000000000000001100 :
 b00000000000000000000000000000110 9

test_regress/t/t_trace_complex_structs.out

@@ -1,10 +1,10 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
+  $var wire 1 I clk $end
   $scope module $unit $end
    $var wire 1 # global_bit $end
   $upscope $end
-  $var wire 1 I clk $end
   $scope module t $end
    $var wire 1 I clk $end
    $var wire 32 $ cyc [31:0] $end

test_regress/t/t_trace_complex_structs_fst.out

@@ -1,5 +1,5 @@
 $date
-	Thu Jan 25 08:09:51 2024
+	Tue Jun 10 19:02:40 2025
 
 $end
 $version
@@ -11,12 +11,12 @@ $end
 $scope module top $end
 $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
 $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
+$var wire 1 ! clk $end
 $scope module $unit $end
-$var bit 1 ! global_bit $end
+$var bit 1 " global_bit $end
 $upscope $end
-$var wire 1 " clk $end
 $scope module t $end
-$var wire 1 " clk $end
+$var wire 1 ! clk $end
 $var integer 32 # cyc [31:0] $end
 $scope struct v_strp $end
 $var bit 1 $ b1 $end
@@ -151,11 +151,11 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000000 #
-0"
+1"
-1!
+0!
 $end
 #10
-1"
+1!
 b00000000000000000000000000000001 #
 1$
 1%
@@ -189,9 +189,9 @@ b111 G
 b00000000000000000000000000000101 N
 b00000000000000000000000000000101 O
 #15
-0"
+0!
 #20
-1"
+1!
 b110 G
 b00000000000000000000000000000100 F
 b00000000000000000000000000000010 E
@@ -225,9 +225,9 @@ b00000000000000000000000000000010 #
 b111 H
 b111 I
 #25
-0"
+0!
 #30
-1"
+1!
 b110 I
 b110 H
 b00000000000000000000000000000011 #
@@ -261,9 +261,9 @@ b00000000000000000000000000000011 E
 b00000000000000000000000000000110 F
 b101 G
 #35
-0"
+0!
 #40
-1"
+1!
 b100 G
 b00000000000000000000000000001000 F
 b00000000000000000000000000000100 E
@@ -297,9 +297,9 @@ b00000000000000000000000000000100 #
 b101 H
 b101 I
 #45
-0"
+0!
 #50
-1"
+1!
 b100 I
 b100 H
 b00000000000000000000000000000101 #
@@ -333,9 +333,9 @@ b00000000000000000000000000000101 E
 b00000000000000000000000000001010 F
 b011 G
 #55
-0"
+0!
 #60
-1"
+1!
 b010 G
 b00000000000000000000000000001100 F
 b00000000000000000000000000000110 E

test_regress/t/t_trace_event.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module t $end
   $var event 1 # ev_test $end
   $var wire 32 $ i [31:0] $end

test_regress/t/t_trace_event_fst.out

@@ -1,5 +1,5 @@
 $date
-	Sun Sep 22 22:54:12 2024
+	Tue Jun 10 19:02:19 2025
 
 $end
 $version
@@ -8,8 +8,6 @@ $end
 $timescale
 	1ps
 $end
-$scope module $rootio $end
-$upscope $end
 $scope module t $end
 $var event 1 ! ev_test $end
 $var int 32 " i [31:0] $end

test_regress/t/t_trace_no_top_name.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module another_top $end
   $var wire 1 # b $end
  $upscope $end

test_regress/t/t_trace_no_top_name2.v

@@ -4,6 +4,14 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+package foo_pkg;
+   function int foo_func;
+      input int b;
+      int b_current;
+      return 0;
+   endfunction
+endpackage
+
 module sub;
    int a = 1212;
 endmodule
@@ -13,7 +21,9 @@ module t (/*AUTOARG*/
    clk
    );
    input clk;
-   int   cyc;
+   int cyc;
+
+   import foo_pkg::*;
 
    sub sub();
 

test_regress/t/t_trace_no_top_name2_fst.out

@@ -1,5 +1,5 @@
 $date
-	Sat Sep 21 08:10:39 2024
+	Tue Jun 10 18:57:59 2025
 
 $end
 $version
@@ -11,67 +11,71 @@ $end
 $scope module $rootio $end
 $var wire 1 ! clk $end
 $upscope $end
+$scope module foo_pkg $end
+$var int 32 " foo_func__Vstatic__b_current [31:0] $end
+$upscope $end
 $scope module t $end
 $var wire 1 ! clk $end
-$var int 32 " cyc [31:0] $end
+$var int 32 # cyc [31:0] $end
 $scope module sub $end
-$var int 32 # a [31:0] $end
+$var int 32 $ a [31:0] $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b00000000000000000000010010111100 #
+b00000000000000000000010010111100 $
+b00000000000000000000000000000000 #
 b00000000000000000000000000000000 "
 0!
 $end
 #1
 1!
-b00000000000000000000000000000001 "
+b00000000000000000000000000000001 #
 #2
 0!
 #3
 1!
-b00000000000000000000000000000010 "
+b00000000000000000000000000000010 #
 #4
 0!
 #5
 1!
-b00000000000000000000000000000011 "
+b00000000000000000000000000000011 #
 #6
 0!
 #7
 1!
-b00000000000000000000000000000100 "
+b00000000000000000000000000000100 #
 #8
 0!
 #9
 1!
-b00000000000000000000000000000101 "
+b00000000000000000000000000000101 #
 #10
 0!
 #11
 1!
-b00000000000000000000000000000110 "
+b00000000000000000000000000000110 #
 #12
 0!
 #13
 1!
-b00000000000000000000000000000111 "
+b00000000000000000000000000000111 #
 #14
 0!
 #15
 1!
-b00000000000000000000000000001000 "
+b00000000000000000000000000001000 #
 #16
 0!
 #17
 1!
-b00000000000000000000000000001001 "
+b00000000000000000000000000001001 #
 #18
 0!
 #19
 1!
-b00000000000000000000000000001010 "
+b00000000000000000000000000001010 #
 #20
 0!

test_regress/t/t_trace_no_top_name2_saif.out

@@ -11,6 +11,42 @@
    (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20))
   )
  )
+ (INSTANCE foo_pkg
+  (NET
+   (foo_func__Vstatic__b_current\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   (foo_func__Vstatic__b_current\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+  )
+ )
  (INSTANCE t
   (NET
    (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20))

test_regress/t/t_trace_no_top_name2_vcd.out

@@ -3,6 +3,9 @@ $timescale 1ps $end
  $scope module $rootio $end
   $var wire 1 # clk $end
  $upscope $end
+ $scope module foo_pkg $end
+  $var wire 32 & foo_func__Vstatic__b_current [31:0] $end
+ $upscope $end
  $scope module t $end
   $var wire 1 # clk $end
   $var wire 32 $ cyc [31:0] $end
@@ -17,6 +20,7 @@ $enddefinitions $end
 0#
 b00000000000000000000000000000000 $
 b00000000000000000000010010111100 %
+b00000000000000000000000000000000 &
 #1
 1#
 b00000000000000000000000000000001 $

test_regress/t/t_trace_param_override.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module t $end
   $var wire 32 # POVERRODE [31:0] $end
   $var wire 32 $ PORIG [31:0] $end

test_regress/t/t_trace_public.out

@@ -1,6 +1,8 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
+  $var wire 1 5 CLK $end
+  $var wire 1 6 RESET $end
   $scope module t $end
    $var wire 1 5 CLK $end
    $var wire 1 # RESET $end
@@ -23,8 +25,6 @@ $timescale 1ps $end
     $var wire 128 1 i128 [63:-64] $end
    $upscope $end
   $upscope $end
-  $var wire 1 5 CLK $end
-  $var wire 1 6 RESET $end
  $upscope $end
 $enddefinitions $end
 

test_regress/t/t_trace_timing1.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
- $scope module $rootio $end
- $upscope $end
  $scope module t $end
   $var wire 32 % CLOCK_CYCLE [31:0] $end
   $var wire 1 # rst $end