Fix class parameter resolution

Signed-off-by: Andrii Andrieiev <aandrieiev@internships.antmicro.com>

docs/CONTRIBUTORS

@@ -26,6 +26,7 @@ Andrei Kostovski
 Andrew Miloradovsky
 Andrew Nolte
 Andrew Voznytsa
+Andrii Andrieiev
 anonkey
 Anthony Donlon
 Anthony Moore

src/V3LinkDot.cpp

@@ -6126,11 +6126,10 @@ class LinkDotResolveVisitor final : public VNVisitor {
         // Only emit error if the child is not a type.
         // Do NOT unwrap valid types here - leave that to V3Width.
         // Unwrapping here breaks type parameter resolution during cloning.
-        if (nodep->lhsp() && !VN_IS(nodep->lhsp(), NodeDType)) {
+        if (nodep->lhsp() && !VN_IS(nodep->lhsp(), NodeDType) && !VN_IS(nodep->lhsp(), Dot)) {
             // Not a type - emit error
-            if (AstConst* const constp = VN_CAST(nodep->lhsp(), Const)) {
-                nodep->lhsp()->v3error(
-                    "Expecting a data type, not a constant: " << constp->toSInt());
+            if (VN_IS(nodep->lhsp(), Const)) {
+                nodep->lhsp()->v3error("Expecting a data type, not a constant");
             } else {
                 nodep->lhsp()->v3error("Expecting a data type, not "
                                        << nodep->lhsp()->typeName() << ": '"

test_regress/t/t_interface_typedef3.out

@@ -1,5 +0,0 @@
-%Error: t/t_interface_typedef3.v:22:19: Expecting a data type, not DOT: ''
-   22 |   typedef iface_mp.choice_t tdef_t;
-      |                   ^
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: Exiting due to

test_regress/t/t_interface_typedef3.py

@@ -9,13 +9,10 @@
 
 import vltest_bootstrap
 
-test.scenarios('simulator_st')
+test.scenarios('simulator')
 
-test.compile(verilator_flags2=['--binary'],
-             fails=test.vlt_all,
-             expect_filename=test.golden_filename)
+test.compile()
 
-if not test.vlt_all:
-    test.execute()
+test.execute()
 
 test.passes()

test_regress/t/t_interface_typedef3.v

@@ -20,7 +20,7 @@ module sub (
     interface.mp iface_mp
 );
   typedef iface_mp.choice_t tdef_t;
-  tdef_t P;
+  tdef_t P = '1;
   initial begin
     `checkd($bits(tdef_t), 4);
   end
@@ -29,4 +29,9 @@ endmodule
 module t;
   ifc u_ifc ();
   sub u_sub (u_ifc.mp);
+  initial begin
+    if (u_sub.P != '1) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule

test_regress/t/t_interface_typedef_bad.out

@@ -2,13 +2,10 @@
    15 |   typedef not_found.choice_t choice1_t;   
       |           ^~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_interface_typedef_bad.v:15:20: Expecting a data type, not a constant: 0
+%Error: t/t_interface_typedef_bad.v:15:20: Expecting a data type, not a constant
    15 |   typedef not_found.choice_t choice1_t;   
       |                    ^
-%Error: t/t_interface_typedef_bad.v:16:12: Expecting a data type, not DOT: ''
-   16 |   typedef i.not_found_t choice2_t;   
-      |            ^
-%Error: t/t_interface_typedef_bad.v:17:19: Expecting a data type, not MEMBERSEL: 'x_t'
-   17 |   typedef not_ifc.x_t choice3_t;   
+%Error: t/t_interface_typedef_bad.v:16:19: Expecting a data type, not MEMBERSEL: 'x_t'
+   16 |   typedef not_ifc.x_t choice2_t;   
       |                   ^~~
 %Error: Exiting due to

test_regress/t/t_interface_typedef_bad.v

@@ -13,8 +13,7 @@ module sub (
 );
   logic not_ifc;
   typedef not_found.choice_t choice1_t;  // <--- Error: not found interface port
-  typedef i.not_found_t choice2_t;  // <--- Error: not found typedef
-  typedef not_ifc.x_t choice3_t;  // <--- Error: sub not interface reference
+  typedef not_ifc.x_t choice2_t;  // <--- Error: sub not interface reference
 endmodule
 
 module t;

test_regress/t/t_interface_typedef_bad2.out

@@ -0,0 +1,10 @@
+%Error: t/t_interface_typedef_bad2.v:15:13: Can't find definition of 'not_found_t' in dotted variable/method: 'i.not_found_t'
+                                          : ... note: In instance 't.u_sub'
+   15 |   typedef i.not_found_t choice_t;   
+      |             ^~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_interface_typedef_bad2.v:15:12: Expecting a data type, not a constant
+                                          : ... note: In instance 't.u_sub'
+   15 |   typedef i.not_found_t choice_t;   
+      |            ^
+%Error: Exiting due to

test_regress/t/t_interface_typedef_bad2.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_interface_typedef_bad2.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+interface ifc;
+  integer i;
+endinterface
+
+module sub (
+    interface i
+);
+  logic not_ifc;
+  typedef i.not_found_t choice_t;  // <--- Error: not found typedef
+endmodule
+
+module t;
+  ifc u_ifc ();
+  sub u_sub (u_ifc);
+endmodule

test_regress/t/t_param_type_bad.out

@@ -1,4 +1,4 @@
-%Error: t/t_param_type_bad.v:9:26: Expecting a data type, not a constant: 2
+%Error: t/t_param_type_bad.v:9:26: Expecting a data type, not a constant
     9 |   localparam type bad2 = 2;   
       |                          ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

test_regress/t/t_param_type_dot.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_param_type_dot.v

@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+class C;
+  typedef logic [1:0] T;
+  class nst;
+    typedef logic [2:0] S;
+  endclass
+endclass: C
+
+class P#(type C);
+  localparam type C1_t = C::T;
+  parameter type C2_t = C::nst::S;
+  C1_t x = '1;
+  C2_t y = '1;
+endclass : P
+
+module t();
+  P#(C) P_data = new();
+  initial begin
+    if (P_data.x != '1) $stop;
+    if (P_data.y != '1) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule

test_regress/t/t_param_type_dot_bad.out

@@ -0,0 +1,14 @@
+%Error: t/t_param_type_dot_bad.v:13:26: Found definition of 'C' as a PARAMTYPEDTYPE but expected a scope/variable
+   13 |   localparam type C1_t = C.T;
+      |                          ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_param_type_dot_bad.v:13:27: Expecting a data type, not a constant
+   13 |   localparam type C1_t = C.T;
+      |                           ^
+%Error: t/t_param_type_dot_bad.v:14:25: Found definition of 'C' as a PARAMTYPEDTYPE but expected a scope/variable
+   14 |   parameter type C2_t = C.y;
+      |                         ^
+%Error: t/t_param_type_dot_bad.v:14:26: Expecting a data type, not a constant
+   14 |   parameter type C2_t = C.y;
+      |                          ^
+%Error: Exiting due to

test_regress/t/t_param_type_dot_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_param_type_dot_bad.v

@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+class C;
+  typedef logic [1:0] T;
+  static int y = 1;
+endclass: C
+
+class P#(type C);
+  localparam type C1_t = C.T;
+  parameter type C2_t = C.y;
+  C1_t x = '1;
+  C2_t y = 2;
+endclass : P
+
+module t();
+  P#(C) P_data = new();
+  initial begin
+    if (P_data.x != '1) $stop;
+    if (P_data.y != 2) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule