Misc internal coverage improvements.

nodist/code_coverage.dat

@@ -42,6 +42,6 @@ remove_source("*examples/*");
 # Would just be removed with remove_source in later step
 remove_gcda_regexp(qr!test_regress/.*/(Vt_|Vtop_).*\.gcda!);
 
-exclude_line_regexp(qr/(\bv3fatalSrc\b|\bVL_UNCOVERABLE\b|\bVL_FATAL|\bUASSERT\bERROR_RSVD_WORD)/);
+exclude_line_regexp(qr/(\bv3fatalSrc\b|\bVL_UNCOVERABLE\b|\bVL_FATAL|\bUASSERT\bERROR_RSVD_WORD\bV3ERROR_NA)/);
 
 1;

src/V3Delayed.cpp

@@ -457,7 +457,7 @@ private:
         }
     }
 
-    virtual void visit(AstNodeFor* nodep) VL_OVERRIDE {
+    virtual void visit(AstNodeFor* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc(
             "For statements should have been converted to while statements in V3Begin");
     }

src/V3EmitC.cpp

@@ -363,7 +363,7 @@ public:
     virtual void visit(AstIntfRef* nodep) VL_OVERRIDE {
         putsQuoted(VIdProtect::protectWordsIf(AstNode::vcdName(nodep->name()), nodep->protect()));
     }
-    virtual void visit(AstNodeCase* nodep) VL_OVERRIDE {
+    virtual void visit(AstNodeCase* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         // In V3Case...
         nodep->v3fatalSrc("Case statements should have been reduced out");
     }

src/V3InstrCount.cpp

@@ -139,10 +139,10 @@ private:
         iterateAndNextNull(nodep->lsbp());
         iterateAndNextNull(nodep->widthp());
     }
-    virtual void visit(AstSliceSel* nodep) VL_OVERRIDE {
+    virtual void visit(AstSliceSel* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc("AstSliceSel unhandled");
     }
-    virtual void visit(AstMemberSel* nodep) VL_OVERRIDE {
+    virtual void visit(AstMemberSel* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc("AstMemberSel unhandled");
     }
     virtual void visit(AstConcat* nodep) VL_OVERRIDE {

src/V3LinkResolve.cpp

@@ -212,7 +212,7 @@ private:
             nodep->v3error("Unsupported: Complex statement in sensitivity list");
         }
     }
-    virtual void visit(AstSenGate* nodep) VL_OVERRIDE {
+    virtual void visit(AstSenGate* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc("SenGates shouldn't be in tree yet");
     }
 

src/V3Param.cpp

@@ -486,7 +486,7 @@ private:
             m_generateHierName = rootHierName;
         }
     }
-    virtual void visit(AstGenFor* nodep) VL_OVERRIDE {
+    virtual void visit(AstGenFor* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc("GENFOR should have been wrapped in BEGIN");
     }
     virtual void visit(AstGenCase* nodep) VL_OVERRIDE {

src/V3Scope.cpp

@@ -189,7 +189,7 @@ private:
     virtual void visit(AstCellInline* nodep) VL_OVERRIDE {  //
         nodep->scopep(m_scopep);
     }
-    virtual void visit(AstActive* nodep) VL_OVERRIDE {
+    virtual void visit(AstActive* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc("Actives now made after scoping");
     }
     virtual void visit(AstNodeProcedure* nodep) VL_OVERRIDE {

src/V3String.cpp

@@ -66,10 +66,6 @@ bool VString::wildmatch(const string& s, const string& p) {
     return wildmatch(s.c_str(), p.c_str());
 }
 
-bool VString::isWildcard(const string& p) {
-    return ((p.find('*') != string::npos) || (p.find('?') != string::npos));
-}
-
 string VString::dot(const string& a, const string& dot, const string& b) {
     if (b == "") return a;
     if (a == "") return b;

src/V3String.h

@@ -74,8 +74,6 @@ public:
     static bool wildmatch(const char* s, const char* p);
     // Return true if p with ? or *'s matches s
     static bool wildmatch(const string& s, const string& p);
-    // Return true if this is a wildcard string (contains * or ?)
-    static bool isWildcard(const string& p);
     // Return {a}{dot}{b}, omitting dot if a or b are empty
     static string dot(const string& a, const string& dot, const string& b);
     // Convert string to lowercase (tolower)

src/V3Task.cpp

@@ -1335,7 +1335,7 @@ private:
         // Done the loop
         m_insStmtp = NULL;  // Next thing should be new statement
     }
-    virtual void visit(AstNodeFor* nodep) VL_OVERRIDE {
+    virtual void visit(AstNodeFor* nodep) VL_OVERRIDE {  // LCOV_EXCL_LINE
         nodep->v3fatalSrc(
             "For statements should have been converted to while statements in V3Begin.cpp");
     }
@@ -1506,12 +1506,12 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
         }
     }
 
-    if (debug() >= 9) {
+    if (debug() >= 9) {  // LCOV_EXCL_START
         nodep->dumpTree(cout, "-ftref-out: ");
         for (int i = 0; i < tpinnum; ++i) {
             UINFO(0, "   pin " << i << "  conn=" << cvtToHex(tconnects[i].second) << endl);
         }
-    }
+    }  // LCOV_EXCL_END
     return tconnects;
 }
 

src/VlcTest.h

@@ -74,7 +74,7 @@ public:
     void dump(bool bucketsToo) {
         if (testrun() || computrons() != 0.0) {  // currently unused // LCOV_EXCL_LINE
             cout << "  " << std::setw(8) << std::setfill('0') << testrun()  // LCOV_EXCL_LINE
-                 << ",  " << std::setw(7) << std::setfill(' ') << computrons()
+                 << ",  " << std::setw(7) << std::setfill(' ') << computrons()  // LCOV_EXCL_LINE
                  << ",";  // LCOV_EXCL_LINE
         }
         cout << "  " << std::setw(7) << std::setfill(' ') << bucketsCovered();

src/VlcTop.cpp

@@ -170,8 +170,8 @@ void VlcTop::rank() {
     // solution and move up to larger subset of tests.  (Aka quick sort.)
     while (true) {
         if (debug()) {
-            UINFO(9, "Left on iter" << nextrank << ": ");
+            UINFO(9, "Left on iter" << nextrank << ": ");  // LCOV_EXCL_LINE
-            remaining.dump();
+            remaining.dump();  // LCOV_EXCL_LINE
         }
         VlcTest* bestTestp = NULL;
         vluint64_t bestRemain = 0;

test_regress/t/t_cdc_async_debug_bad.out

@@ -0,0 +1,20 @@
+Edge Report for Vt_cdc_async_debug_bad
+  t_cdc_async_bad.v:    input     clk                                       SRC=@(*)  DST=@(posedge clk or negedge rst0_n or negedge t.__Vcellinp__flop4__rst_n or negedge t.rst1_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n)
+  t_cdc_async_bad.v:    input     d                                         SRC=@(*)  DST=@(posedge clk or negedge rst0_n or negedge t.__Vcellinp__flop4__rst_n or negedge t.rst1_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n)
+  t_cdc_async_bad.v:    input     rst0_n                                    SRC=@(*)  DST=@(posedge clk or negedge rst0_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n)
+  t_cdc_async_bad.v:    output    q0                                        SRC=@(posedge clk or negedge rst0_n)  DST=
+  t_cdc_async_bad.v:    output    q1                                        SRC=@(posedge clk or negedge t.rst1_n)  DST=
+  t_cdc_async_bad.v:    output    q2                                        SRC=@(posedge clk or negedge t.rst2_bad_n)  DST=
+  t_cdc_async_bad.v:    output    q3                                        SRC=@(posedge clk or negedge t.rst2_bad_n)  DST=
+  t_cdc_async_bad.v:    output    q4                                        SRC=@(posedge clk or negedge t.__Vcellinp__flop4__rst_n)  DST=
+  t_cdc_async_bad.v:    output    q5                                        SRC=@(posedge clk or negedge t.rst5_waive_n)  DST=
+  t_cdc_async_bad.v:    output    q6a                                       SRC=@(posedge clk or negedge t.rst6a_bad_n)  DST=
+  t_cdc_async_bad.v:    output    q6b                                       SRC=@(posedge clk or negedge t.rst6b_bad_n)  DST=
+  t_cdc_async_bad.v:    wire      t.__Vcellinp__flop4__rst_n                SRC=@(posedge clk)  DST=@(posedge clk or negedge t.__Vcellinp__flop4__rst_n)
+  t_cdc_async_bad.v:    wire      t.rst1_n                                  SRC=@(posedge clk)  DST=@(posedge clk or negedge t.rst1_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n)
+  t_cdc_async_bad.v:    wire      t.rst2_bad_n                              SRC=@(* or posedge clk)  DST=@(posedge clk or negedge t.rst2_bad_n)
+  t_cdc_async_bad.v:    wire      t.rst4_n                                  SRC=@(posedge clk)  DST=@(posedge clk or negedge t.__Vcellinp__flop4__rst_n)
+  t_cdc_async_bad.v:    wire      t.rst5_waive_n                            SRC=@(* or posedge clk)  DST=@(posedge clk or negedge t.rst5_waive_n)
+  t_cdc_async_bad.v:    wire      t.rst6_bad_n                              SRC=@(* or posedge clk)  DST=@(posedge clk or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n)
+  t_cdc_async_bad.v:    wire      t.rst6a_bad_n                             SRC=@(* or posedge clk)  DST=@(posedge clk or negedge t.rst6a_bad_n)
+  t_cdc_async_bad.v:    wire      t.rst6b_bad_n                             SRC=@(* or posedge clk)  DST=@(posedge clk or negedge t.rst6b_bad_n)

test_regress/t/t_cdc_async_debug_bad.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+top_filename("t/t_cdc_async_bad.v");
+
+compile(
+    # --debug so we get code coverage of Cdc
+    v_flags => ['--cdc --debug'],
+    verilator_make_gmake => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    fails => 1,
+    );
+
+files_identical("$Self->{obj_dir}/V$Self->{name}__cdc_edges.txt", $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_dpi_export_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_dpi_export_bad.v:10:24: Can't find definition of exported task/function: 'dpix_bad_missing'
+   10 |    export "DPI-C" task dpix_bad_missing;
+      |                        ^~~~~~~~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_dpi_export_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_dpi_export_bad.v

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Copyright 2009 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module t;
+   export "DPI-C" task dpix_bad_missing;
+endmodule

test_regress/t/t_flag_build_bad2.pl

@@ -0,0 +1,26 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+top_filename("t/t_flag_make_cmake.v");
+
+compile(
+    verilator_make_cmake => 0,
+    verilator_make_gmake => 0,
+    # Need --no-print-directory so golden file doesn't compare directory names
+    verilator_flags2 => ["--build --MAKEFLAGS --no-print-directory"
+                         ." --MAKEFLAGS illegal-flag-to-fail-make"],
+    fails => 1,
+    # Recursive make breaks the golden compare
+    #expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_package_export.v

@@ -40,6 +40,9 @@ package pkg30;
 `ifdef T_PACKAGE_EXPORT
    export pkg1::PARAM2;
    export pkg1::PARAM3;
+`endif
+`ifdef T_PACKAGE_EXPORT_BAD
+   export pkg1::BAD_DOES_NOT_EXIST;
 `endif
    parameter PARAM1 = 8;
 endpackage

test_regress/t/t_package_export_bad.out

@@ -1,25 +1,28 @@
-%Error: t/t_package_export.v:57:16: Can't find definition of scope/variable: 'PARAM2'
+%Error: t/t_package_export.v:45:17: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST'
+   45 |    export pkg1::BAD_DOES_NOT_EXIST;
+      |                 ^~~~~~~~~~~~~~~~~~
+%Error: t/t_package_export.v:60:16: Can't find definition of scope/variable: 'PARAM2'
                                   : ... Suggested alternative: 'PARAM1'
-   57 |    reg [pkg11::PARAM2 : 0] bus12;
+   60 |    reg [pkg11::PARAM2 : 0] bus12;
       |                ^~~~~~
-%Error: t/t_package_export.v:58:16: Can't find definition of scope/variable: 'PARAM3'
+%Error: t/t_package_export.v:61:16: Can't find definition of scope/variable: 'PARAM3'
                                   : ... Suggested alternative: 'PARAM1'
-   58 |    reg [pkg11::PARAM3 : 0] bus13;
+   61 |    reg [pkg11::PARAM3 : 0] bus13;
       |                ^~~~~~
-%Error: t/t_package_export.v:61:16: Can't find definition of scope/variable: 'PARAM2'
+%Error: t/t_package_export.v:64:16: Can't find definition of scope/variable: 'PARAM2'
                                   : ... Suggested alternative: 'PARAM1'
-   61 |    reg [pkg21::PARAM2 : 0] bus22;
+   64 |    reg [pkg21::PARAM2 : 0] bus22;
       |                ^~~~~~
-%Error: t/t_package_export.v:62:16: Can't find definition of scope/variable: 'PARAM3'
+%Error: t/t_package_export.v:65:16: Can't find definition of scope/variable: 'PARAM3'
                                   : ... Suggested alternative: 'PARAM1'
-   62 |    reg [pkg21::PARAM3 : 0] bus23;
+   65 |    reg [pkg21::PARAM3 : 0] bus23;
       |                ^~~~~~
-%Error: t/t_package_export.v:65:16: Can't find definition of scope/variable: 'PARAM2'
+%Error: t/t_package_export.v:68:16: Can't find definition of scope/variable: 'PARAM2'
                                   : ... Suggested alternative: 'PARAM1'
-   65 |    reg [pkg31::PARAM2 : 0] bus32;
+   68 |    reg [pkg31::PARAM2 : 0] bus32;
       |                ^~~~~~
-%Error: t/t_package_export.v:66:16: Can't find definition of scope/variable: 'PARAM3'
+%Error: t/t_package_export.v:69:16: Can't find definition of scope/variable: 'PARAM3'
                                   : ... Suggested alternative: 'PARAM1'
-   66 |    reg [pkg31::PARAM3 : 0] bus33;
+   69 |    reg [pkg31::PARAM3 : 0] bus33;
       |                ^~~~~~
 %Error: Exiting due to

test_regress/t/t_udp.out

@@ -0,0 +1,4 @@
+%Error: t/t_udp.v:104:4: Unsupported: Verilog 1995 UDP Tables.  Use --bbox-unsup to ignore tables.
+  104 |    table
+      |    ^~~~~
+%Error: Exiting due to

test_regress/t/t_udp.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+top_filename("t/t_udp.v");
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_udp_bad.out

@@ -1,4 +1,17 @@
-%Error: t/t_udp.v:104:4: Unsupported: Verilog 1995 UDP Tables.  Use --bbox-unsup to ignore tables.
+%Warning-PINMISSING: t/t_udp_bad.v:10:10: Cell has missing pin: 'c_bad'
-  104 |    table
+   10 |    udp_x x (a, b);
-      |    ^~~~~
+      |          ^
+                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
+%Error: t/t_udp_bad.v:14:18: Pin is not an in/out/inout/interface: 'a_bad'
+   14 | primitive udp_x (a_bad, b, c_bad);
+      |                  ^~~~~
+%Error: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1'
+   10 |    udp_x x (a, b);
+      |             ^
+%Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules
+   15 |    tri  a_bad;
+      |         ^~~~~
+%Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules
+   17 |    output c_bad;
+      |           ^~~~~
 %Error: Exiting due to

test_regress/t/t_udp_bad.pl

@@ -8,17 +8,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(simulator => 1);
+scenarios(linter => 1);
 
-top_filename("t/t_udp.v");
+lint(
-
+    verilator_flags2 => ["--lint-only --bbox-unsup"],
-compile(
     fails => $Self->{vlt_all},
     expect_filename => $Self->{golden_filename},
     );
 
-execute(
-    ) if !$Self->{vlt_all};
-
 ok(1);
 1;

test_regress/t/t_udp_bad.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   wire a, b;
+   udp_x x (a, b);
+
+endmodule
+
+primitive udp_x (a_bad, b, c_bad);
+   tri  a_bad;
+   output b;
+   output c_bad;
+   table
+      //a   b
+      0  :   1;
+      1  :   0;
+   endtable
+endprimitive