Add unsupported for loops error, msg2692.
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@ -11,6 +11,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Add circular typedef error, bug1388. [Al Grant]
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**** Add circular typedef error, bug1388. [Al Grant]
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**** Add unsupported for loops error, msg2692. [Yu Sheng Lin]
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**** Fix FST tracing of wide arrays, bug1376. [Aleksander Osman]
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**** Fix FST tracing of wide arrays, bug1376. [Aleksander Osman]
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**** Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]
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**** Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]
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@ -2647,13 +2647,29 @@ assignment_pattern<patternp>: // ==IEEE: assignment_pattern
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// "datatype id = x {, id = x }" | "yaId = x {, id=x}" is legal
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// "datatype id = x {, id = x }" | "yaId = x {, id=x}" is legal
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for_initialization<nodep>: // ==IEEE: for_initialization + for_variable_declaration + extra terminating ";"
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for_initialization<nodep>: // ==IEEE: for_initialization + for_variable_declaration + extra terminating ";"
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// // IEEE: for_variable_declaration
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// // IEEE: for_variable_declaration
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data_type idAny/*new*/ '=' expr ';'
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for_initializationItemList ';' { $$ = $1; }
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// // IEEE: 1800-2017 empty initialization
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| ';' { $$ = NULL; }
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;
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for_initializationItemList<nodep>: // IEEE: [for_variable_declaration...]
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for_initializationItem { $$ = $1; }
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| for_initializationItemList ',' for_initializationItem { $$ = $1; $<fl>2->v3error("Unsupported: for loop initialization after the first comma"); }
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;
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for_initializationItem<nodep>: // IEEE: variable_assignment + for_variable_declaration
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// // IEEE: for_variable_declaration
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data_type idAny/*new*/ '=' expr
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{ VARRESET_NONLIST(VAR); VARDTYPE($1);
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{ VARRESET_NONLIST(VAR); VARDTYPE($1);
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$$ = VARDONEA($<fl>2,*$2,NULL,NULL);
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$$ = VARDONEA($<fl>2,*$2,NULL,NULL);
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$$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));}
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$$->addNext(new AstAssign($3, new AstVarRef($3,*$2,true), $4));}
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| varRefBase '=' expr ';' { $$ = new AstAssign($2,$1,$3); }
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// // IEEE-2012:
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| ';' { $$ = NULL; }
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| yVAR data_type idAny/*new*/ '=' expr
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//UNSUP: List of initializations
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{ VARRESET_NONLIST(VAR); VARDTYPE($2);
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$$ = VARDONEA($<fl>3,*$3,NULL,NULL);
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$$->addNext(new AstAssign($4, new AstVarRef($4,*$3,true), $5));}
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// // IEEE: variable_assignment
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| varRefBase '=' expr { $$ = new AstAssign($2, $1, $3); }
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;
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;
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for_stepE<nodep>: // IEEE: for_step + empty
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for_stepE<nodep>: // IEEE: for_step + empty
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@ -2662,8 +2678,8 @@ for_stepE<nodep>: // IEEE: for_step + empty
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;
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;
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for_step<nodep>: // IEEE: for_step
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for_step<nodep>: // IEEE: for_step
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//UNSUP: List of steps, instead we keep it simple
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genvar_iteration { $$ = $1; }
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genvar_iteration { $$ = $1; }
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| for_step ',' genvar_iteration { $$ = $1; $<fl>1->v3error("Unsupported: for loop step after the first comma"); }
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;
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;
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loop_variables<nodep>: // IEEE: loop_variables
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loop_variables<nodep>: // IEEE: loop_variables
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@ -0,0 +1,10 @@
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%Error: t/t_for_comma_bad.v:13: Unsupported: for loop step after the first comma
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%Error: t/t_for_comma_bad.v:16: Unsupported: for loop step after the first comma
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%Error: t/t_for_comma_bad.v:19: Unsupported: for loop step after the first comma
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%Error: t/t_for_comma_bad.v:22: Unsupported: for loop step after the first comma
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%Error: t/t_for_comma_bad.v:25: Unsupported: for loop step after the first comma
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%Error: t/t_for_comma_bad.v:26: Unsupported: for loop initialization after the first comma
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%Error: t/t_for_comma_bad.v:27: Unsupported: for loop initialization after the first comma
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%Error: t/t_for_comma_bad.v:28: Unsupported: for loop initialization after the first comma
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%Error: t/t_for_comma_bad.v:28: Unsupported: for loop step after the first comma
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%Error: Exiting due to
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@ -0,0 +1,19 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 'vlt');
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compile(
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v_flags2 => ["--lint-only"],
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -0,0 +1,33 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/);
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integer a, b;
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initial begin
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for (; ; ) ;
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for (; ; a=a+1) ;
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for (; ; a=a+1, b=b+1) ;
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for (; a<1; ) ;
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for (; a<1; a=a+1) ;
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for (; a<1; a=a+1, b=b+1) ;
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for (a=0; a<1; ) ;
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for (a=0; a<1; a=a+1) ;
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for (a=0; a<1; a=a+1, b=b+1) ;
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for (integer a=0; a<1; ) ;
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for (integer a=0; a<1; a=a+1) ;
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for (integer a=0; a<1; a=a+1, b=b+1) ;
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for (var integer a=0; a<1; ) ;
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for (var integer a=0; a<1; a=a+1) ;
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for (var integer a=0; a<1; a=a+1, b=b+1) ;
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for (integer a=0, integer b=0; a<1; ) ;
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for (integer a=0, integer b=0; a<1; a=a+1) ;
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for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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