Fix hang on bad pattern keys, bug1364.

Changes

@@ -11,6 +11,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]
 
+****  Fix hang on bad pattern keys, bug1364. [Matt Myers]
+
 
 * Verilator 4.006 2018-10-27
 

src/V3Width.cpp

@@ -1756,32 +1756,39 @@ private:
 		    AstMemberDType* memp = classp->membersp();
                     AstPatMember* patp = VN_CAST(nodep->itemsp(), PatMember);
 		    for (; memp || patp; ) {
-			if (patp) {
+                        do {
-			    if (patp->keyp()) {
+                            if (patp) {
-                                if (AstText* textp = VN_CAST(patp->keyp(), Text)) {
+                                if (patp->keyp()) {
-				    memp = classp->findMember(textp->text());
+                                    if (AstText* textp = VN_CAST(patp->keyp(), Text)) {
-				    if (!memp) {
+                                        memp = classp->findMember(textp->text());
-					patp->keyp()->v3error("Assignment pattern key '"<<textp->text()<<"' not found as member");
+                                        if (!memp) {
-					continue;
+                                            patp->keyp()->v3error(
-				    }
+                                                "Assignment pattern key '"
-				} else {
+                                                <<textp->text()<<"' not found as member");
-                                    patp->keyp()->v3error("Assignment pattern key not"
+                                            break;
-                                                          " supported/understood: "<<patp->keyp()->prettyTypeName());
+                                        }
-				}
+                                    } else {
-			    }
+                                        patp->keyp()->v3error(
-			}
+                                            "Assignment pattern key not supported/understood: "
-			if (memp && !patp) {
+                                            <<patp->keyp()->prettyTypeName());
-			    // Missing init elements, warn below
+                                    }
-			    memp=NULL; patp=NULL; break;
+                                }
-			} else if (!memp && patp) { patp->v3error("Assignment pattern contains too many elements");
+                            }
-			    memp=NULL; patp=NULL; break;
+                            if (memp && !patp) {
-			} else {
+                                // Missing init elements, warn below
-                            std::pair<PatMap::iterator, bool> ret = patmap.insert(make_pair(memp, patp));
+                                memp=NULL; patp=NULL; break;
-			    if (!ret.second) {
+                            } else if (!memp && patp) {
-                                patp->v3error("Assignment pattern contains duplicate entry: "
+                                patp->v3error("Assignment pattern contains too many elements");
-                                              << VN_CAST(patp->keyp(), Text)->text());
+                                memp=NULL; patp=NULL; break;
-			    }
+                            } else {
-			}
+                                std::pair<PatMap::iterator, bool> ret
+                                    = patmap.insert(make_pair(memp, patp));
+                                if (!ret.second) {
+                                    patp->v3error("Assignment pattern contains duplicate entry: "
+                                                  << VN_CAST(patp->keyp(), Text)->text());
+                                }
+                            }
+                        } while(0);
 			// Next
                         if (memp) memp = VN_CAST(memp->nextp(), MemberDType);
                         if (patp) patp = VN_CAST(patp->nextp(), PatMember);

test_regress/t/t_array_pattern_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    fails => 1,
+    expect =>
+q{%Error: t/t_array_pattern_bad.v:23: Assignment pattern key 'valids' not found as member
+.*%Error: Exiting due to.*},
+    );
+
+ok(1);
+1;

test_regress/t/t_array_pattern_bad.v

@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+// bug1364
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk, res
+   );
+   input clk;
+   input res;
+
+    typedef struct packed {
+        logic [3:0] port_num;
+    } info_t;
+
+    info_t myinfo;
+
+    always_comb
+      myinfo = '{default: '0,
+                 valids: '1};
+
+endmodule