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Internals: Rename implicit_typeE to match Verilog-Perl

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This commit is contained in:
Wilson Snyder
2009-12-17 20:58:14 -05:00
parent ebe8f554c6
commit 45aa8742d8
3 changed files with 37 additions and 23 deletions
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src/V3Number.cpp
+9
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@@ -558,6 +558,15 @@ bool V3Number::isUnknown() const {
}
return false;
}
bool V3Number::isLt(const V3Number& rhs) const {
for (int bit=0; bit<max(this->width(),rhs.width()); bit++) {
if (this->bitIs1(bit) && rhs.bitIs0(bit)) { return 1; }
if (rhs.bitIs1(bit) && this->bitIs0(bit)) { return 0; }
if (this->bitIsXZ(bit)) { return 0; }
if (rhs.bitIsXZ(bit)) { return 0; }
}
return 0;
}
int V3Number::minWidth() const {
for(int bit=width()-1; bit>0; bit--) {