Tests: Fix unsupported items.

test_regress/t/t_sv_cpu_code/ac_dig.sv

@@ -75,7 +75,11 @@ module ac_dig
 
   always_comb
     begin
+`ifdef VERILATOR //TODO
+      dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr     ), .we(we), .re(re) );
+`else
       dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) );
+`endif
 //      dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re );
     end
 

test_regress/t/t_sv_cpu_code/cpu.sv

@@ -223,7 +223,9 @@ module cpu
   mPreAdrDecode_resp busproperty;
   always_comb
     begin: PreAdrDecode
+      // verilator lint_off WIDTH
       busproperty = dbus.mPreAdrDecode( 0, idec_mem_adr );
+      // verilator lint_on WIDTH
     end
 
 endmodule // cpu

test_regress/t/t_sv_cpu_code/genbus_if.sv

@@ -189,7 +189,9 @@ interface genbus_if
                                     output logic   [SMSB:0] re );
     begin
       s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}};
+      // verilator lint_off WIDTH
       s_ws   [id] = ws & {SSIZE{s_sel[id]}};
+      // verilator lint_on WIDTH
 
       mdata  = s_mdata[id] & {16{~rst}};
       adr    = s_adr  [id];

test_regress/t/t_sv_cpu_code/ports.sv

@@ -5,6 +5,12 @@
 
 // Contributed by M W Lund, Atmel Corporation.
 
+`ifdef VERILATOR  //TODO
+ `define PACKED packed
+`else
+ `define  packed
+`endif
+
 module ports
  #( parameter
       ID = 1 )
@@ -35,12 +41,12 @@ module ports
 
 
   // **** Interal Registers ****
-  struct
+  struct `PACKED
   {
     logic [7:0][1:0] in;
     logic [7:0]      dir;
     logic [7:0]      out;
-    struct
+    struct `PACKED
     {
     logic [7:2]      reserved;
     logic            pullupen;