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Tests: Fix more missing internal code coverage

This commit is contained in:
Wilson Snyder 2023-07-27 06:47:37 -04:00
parent 06521f6cf1
commit 446f21d2a0
22 changed files with 321 additions and 41 deletions
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2
include/verilated_vpi.cpp
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@ -2307,7 +2307,7 @@ PLI_INT32 vpi_flush(void) {
VerilatedVpiImp::assertOneCheck();
VL_VPI_ERROR_RESET_();
Verilated::runFlushCallbacks();
return 0;
return 0; // Gcc coverage bug // LCOV_EXCL_LINE
}
PLI_INT32 vpi_mcd_flush(PLI_UINT32 mcd) {

2
test_regress/t/t_assert_imm_nz_bad.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

1
test_regress/t/t_randstate_seed_bad.out
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@ -1,2 +1,3 @@
%Warning: set_randstate ignored as state string not from get_randstate
%Warning: set_randstate ignored as state string not from get_randstate
*-* All Finished *-*

1
test_regress/t/t_randstate_seed_bad.v
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@ -13,6 +13,7 @@ class Cls;
if (s[0] !== "R") $fatal(2, $sformatf("Bad get_randstate = '%s'", s));
set_randstate("000bad"); // Bad
set_randstate("Zdlffjfmkmhodjcnddlffjfmkmhodjcnd"); // Bad
endfunction
endclass

117
test_regress/t/t_sys_readmem.v
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@ -4,6 +4,9 @@
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`ifdef WRITEMEM_BIN
`define READMEMX $readmemb
`define WRITEMEMX $writememb
@ -20,6 +23,10 @@ module t;
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
reg [(32*6)-1:0] hex_align [0:15];
reg [55:0] qdata [0:15];
reg [25:0] idata [0:15];
reg [10:0] sdata [0:15];
reg [6:0] cdata [0:15];
string fns;
`ifdef WRITEMEM_READ_BACK
@ -28,6 +35,10 @@ module t;
reg [5:0] binary_start_tmp [0:15];
reg [175:0] hex_tmp [0:15];
reg [(32*6)-1:0] hex_align_tmp [0:15];
reg [55:0] qdata_tmp [0:15];
reg [25:0] idata_tmp [0:15];
reg [10:0] sdata_tmp [0:15];
reg [6:0] cdata_tmp [0:15];
string fns_tmp;
`endif
// verilator lint_on ASCRANGE
@ -39,13 +50,21 @@ module t;
// Initialize memories to zero,
// avoid differences between 2-state and 4-state.
for (i=0; i<16; i=i+1) begin
binary_start[i] = 6'h0;
hex[i] = 176'h0;
hex_align[i] = {32*6{1'b0}};
binary_start[i] = '0;
hex[i] = '0;
hex_align[i] = '0;
qdata[i] = '0;
idata[i] = '0;
sdata[i] = '0;
cdata[i] = '0;
`ifdef WRITEMEM_READ_BACK
binary_start_tmp[i] = 6'h0;
hex_tmp[i] = 176'h0;
hex_align_tmp[i] = {32*6{1'b0}};
binary_start_tmp[i] = '0;
hex_tmp[i] = '0;
hex_align_tmp[i] = '0;
qdata_tmp[i] = '0;
idata_tmp[i] = '0;
sdata_tmp[i] = '0;
cdata_tmp[i] = '0;
`endif
end
for (i=2; i<16; i=i+1) begin
@ -161,12 +180,92 @@ module t;
end
begin
fns = "t/t_sys_readmem_b.mem";
`ifdef WRITEMEM_READ_BACK
fns_tmp = `OUT_TMP5;
$readmemb(fns, binary_string_tmp);
$readmemh("t/t_sys_readmem_q.mem", qdata_tmp, 0);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP5);
`endif
`WRITEMEMX(`OUT_TMP5, qdata_tmp, 0);
`READMEMX(`OUT_TMP5, qdata, 0);
`else
$readmemh("t/t_sys_readmem_q.mem", qdata, 0);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, qdata[i]);
`endif
`checkh(qdata['h04], 56'hdcba9876540004);
`checkh(qdata['h0a], 56'hdcba987654000a);
`checkh(qdata['h0b], 56'hdcba987654000b);
`checkh(qdata['h0c], 56'hdcba987654000c);
end
begin
`ifdef WRITEMEM_READ_BACK
$readmemh("t/t_sys_readmem_i.mem", idata_tmp, 0);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP6);
`endif
`WRITEMEMX(`OUT_TMP6, idata_tmp, 0);
`READMEMX(`OUT_TMP6, idata, 0);
`else
$readmemh("t/t_sys_readmem_i.mem", idata, 0);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, idata[i]);
`endif
`checkh(idata['h04], 26'h6540004);
`checkh(idata['h0a], 26'h654000a);
`checkh(idata['h0b], 26'h654000b);
`checkh(idata['h0c], 26'h654000c);
end
begin
`ifdef WRITEMEM_READ_BACK
$readmemh("t/t_sys_readmem_s.mem", sdata_tmp, 0);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP7);
`endif
`WRITEMEMX(`OUT_TMP7, sdata_tmp, 0);
`READMEMX(`OUT_TMP7, sdata, 0);
`else
$readmemh("t/t_sys_readmem_s.mem", sdata, 0);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, sdata[i]);
`endif
`checkh(sdata['h04], 11'h654);
`checkh(sdata['h0a], 11'h65a);
`checkh(sdata['h0b], 11'h65b);
`checkh(sdata['h0c], 11'h65c);
end
begin
`ifdef WRITEMEM_READ_BACK
$readmemh("t/t_sys_readmem_c.mem", cdata_tmp, 0);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP8);
`endif
`WRITEMEMX(`OUT_TMP8, cdata_tmp, 0);
`READMEMX(`OUT_TMP8, cdata, 0);
`else
$readmemh("t/t_sys_readmem_c.mem", cdata, 0);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, cdata[i]);
`endif
`checkh(cdata['h04], 7'h14);
`checkh(cdata['h0a], 7'h1a);
`checkh(cdata['h0b], 7'h1b);
`checkh(cdata['h0c], 7'h1c);
end
begin
fns = "t/t_sys_readmem_b.mem";
`ifdef WRITEMEM_READ_BACK
fns_tmp = `OUT_TMP8;
$readmemb(fns, binary_string_tmp);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP8);
`endif
`WRITEMEMX(fns_tmp, binary_string_tmp);
`READMEMX(fns_tmp, binary_string);

14
test_regress/t/t_sys_readmem_c.mem Normal file
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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@4
14
@a
1a
1b
1c

14
test_regress/t/t_sys_readmem_i.mem Normal file
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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@4
6540004
@a
654000a
654000b
654000c

14
test_regress/t/t_sys_readmem_q.mem Normal file
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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@4
dcba9876540004
@a
dcba987654000a
dcba987654000b
dcba987654000c

14
test_regress/t/t_sys_readmem_s.mem Normal file
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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@4
654
@a
65a
65b
65c

30
test_regress/t/t_sys_writemem.gold5.mem
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@ -1,14 +1,16 @@
02
03
04
05
06
07
10
00
00
00
14
15
00
00
00000000000000
00000000000000
00000000000000
00000000000000
dcba9876540004
00000000000000
00000000000000
00000000000000
00000000000000
00000000000000
dcba987654000a
dcba987654000b
dcba987654000c
00000000000000
00000000000000
00000000000000

16
test_regress/t/t_sys_writemem.gold6.mem Normal file
View File

@ -0,0 +1,16 @@
0000000
0000000
0000000
0000000
2540004
0000000
0000000
0000000
0000000
0000000
254000a
254000b
254000c
0000000
0000000
0000000

16
test_regress/t/t_sys_writemem.gold7.mem Normal file
View File

@ -0,0 +1,16 @@
000
000
000
000
654
000
000
000
000
000
65a
65b
65c
000
000
000

14
test_regress/t/t_sys_writemem.gold8.mem Normal file
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@ -0,0 +1,14 @@
02
03
04
05
06
07
10
00
00
00
14
15
00
00

7
test_regress/t/t_sys_writemem.pl
View File

@ -16,6 +16,8 @@ top_filename("t/t_sys_readmem.v");
# $writememh, to avoid miscompares with X's on 4-state simulators.
$Self->{verilated_randReset} = 2; # 2 == truly random
# TODO make test more generic to take the data type as a define
# then we can call test multiple times in different tests
compile(v_flags2 => [
"+define+WRITEMEM_READ_BACK=1",
"+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"",
@ -23,13 +25,16 @@ compile(v_flags2 => [
"+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"",
"+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"",
"+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"",
"+define+OUT_TMP6=\\\"$Self->{obj_dir}/tmp6.mem\\\"",
"+define+OUT_TMP7=\\\"$Self->{obj_dir}/tmp7.mem\\\"",
"+define+OUT_TMP8=\\\"$Self->{obj_dir}/tmp8.mem\\\"",
]);
execute(
check_finished => 1,
);
for (my $i = 1; $i <= 5; $i++) {
for (my $i = 1; $i <= 8; $i++) {
my $gold = "$Self->{t_dir}/t_sys_writemem.gold${i}.mem";
my $out = "$Self->{obj_dir}/tmp${i}.mem";
files_identical($out, $gold);

30
test_regress/t/t_sys_writemem_b.gold5.mem
View File

@ -1,14 +1,16 @@
000010
000011
000100
000101
000110
000111
010000
000000
000000
000000
010100
010101
000000
000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
11011100101110101001100001110110010101000000000000000100
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
11011100101110101001100001110110010101000000000000001010
11011100101110101001100001110110010101000000000000001011
11011100101110101001100001110110010101000000000000001100
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000

16
test_regress/t/t_sys_writemem_b.gold6.mem Normal file
View File

@ -0,0 +1,16 @@
00000000000000000000000000
00000000000000000000000000
00000000000000000000000000
00000000000000000000000000
10010101000000000000000100
00000000000000000000000000
00000000000000000000000000
00000000000000000000000000
00000000000000000000000000
00000000000000000000000000
10010101000000000000001010
10010101000000000000001011
10010101000000000000001100
00000000000000000000000000
00000000000000000000000000
00000000000000000000000000

16
test_regress/t/t_sys_writemem_b.gold7.mem Normal file
View File

@ -0,0 +1,16 @@
00000000000
00000000000
00000000000
00000000000
11001010100
00000000000
00000000000
00000000000
00000000000
00000000000
11001011010
11001011011
11001011100
00000000000
00000000000
00000000000

14
test_regress/t/t_sys_writemem_b.gold8.mem Normal file
View File

@ -0,0 +1,14 @@
000010
000011
000100
000101
000110
000111
010000
000000
000000
000000
010100
010101
000000
000000

5
test_regress/t/t_sys_writemem_b.pl
View File

@ -24,13 +24,16 @@ compile(v_flags2 => [
"+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"",
"+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"",
"+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"",
"+define+OUT_TMP6=\\\"$Self->{obj_dir}/tmp6.mem\\\"",
"+define+OUT_TMP7=\\\"$Self->{obj_dir}/tmp7.mem\\\"",
"+define+OUT_TMP8=\\\"$Self->{obj_dir}/tmp8.mem\\\"",
]);
execute(
check_finished => 1,
);
for (my $i = 1; $i <= 5; $i++) {
for (my $i = 1; $i <= 8; $i++) {
my $gold = "$Self->{t_dir}/t_sys_writemem_b.gold${i}.mem";
my $out = "$Self->{obj_dir}/tmp${i}.mem";
files_identical($out, $gold);

10
test_regress/t/t_urandom.v
View File

@ -69,6 +69,16 @@ module t(/*AUTOARG*/);
v2 = $urandom();
if (v1 != v2) $stop;
// Seed stability via process.srandom
p.srandom(32'h88888888); // "Large" seed to check a VlRNG::srandom edge case
v1 = $urandom();
p.srandom(32'h88888888);
v2 = $urandom();
if (v1 != v2) $stop;
p.srandom(32'h88888888);
v2 = $urandom();
if (v1 != v2) $stop;
// Seed stability via process.get_randstate
s = p.get_randstate();
v1 = $urandom();

2
test_regress/t/t_vpi_memory.cpp
View File

@ -167,8 +167,10 @@ void _mem_check(const char* name, int size, int left, int right, int words) {
// check vpiRange
TestVpiHandle iter_h = vpi_iterate(vpiRange, mem_h);
TEST_CHECK_NZ(iter_h);
TEST_CHECK_EQ(vpi_get(vpiType, iter_h), vpiIterator);
TestVpiHandle lcl_h = vpi_scan(iter_h);
TEST_CHECK_NZ(lcl_h);
TEST_CHECK_EQ(vpi_get(vpiType, lcl_h), vpiRange);
{
TestVpiHandle side_h = vpi_handle(vpiLeftRange, lcl_h);
TEST_CHECK_NZ(side_h);

7
test_regress/t/t_vpi_var.cpp
View File

@ -325,6 +325,7 @@ int _mon_check_var() {
CHECK_RESULT_NZ(vh10);
vpi_get_value(vh10, &tmpValue);
CHECK_RESULT(tmpValue.value.integer, 4);
CHECK_RESULT(vpi_get(vpiType, vh10), vpiConstant);
p = vpi_get_str(vpiType, vh10);
CHECK_RESULT_CSTR(p, "vpiConstant");
}
@ -386,6 +387,12 @@ int _mon_check_varlist() {
TestVpiHandle vh2 = VPI_HANDLE("sub");
CHECK_RESULT_NZ(vh2);
p = vpi_get_str(vpiName, vh2);
CHECK_RESULT_CSTR(p, "sub");
if (TestSimulator::is_verilator()) {
p = vpi_get_str(vpiDefName, vh2);
CHECK_RESULT_CSTR(p, "<null>"); // Unsupported
}
TestVpiHandle vh10 = vpi_iterate(vpiReg, vh2);
CHECK_RESULT_NZ(vh10);