Fix invalid cast on string structure creation (#4921).
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@ -13,6 +13,8 @@ Verilator 5.023 devel
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**Minor:**
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**Minor:**
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* Fix invalid cast on string structure creation (#4921). [esynr3z]
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Verilator 5.022 2024-02-24
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Verilator 5.022 2024-02-24
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==========================
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==========================
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@ -212,6 +212,11 @@ class CastVisitor final : public VNVisitor {
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void visit(AstCMethodCall* nodep) override {
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void visit(AstCMethodCall* nodep) override {
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iterateChildren(nodep);
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iterateChildren(nodep);
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ensureNullChecked(nodep->fromp());
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ensureNullChecked(nodep->fromp());
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nodep->user1(true);
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}
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void visit(AstCMethodHard* nodep) override {
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iterateChildren(nodep);
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nodep->user1(true);
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}
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}
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void visit(AstMemberSel* nodep) override {
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void visit(AstMemberSel* nodep) override {
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iterateChildren(nodep);
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iterateChildren(nodep);
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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@ -0,0 +1,49 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef string array_of_string_t[];
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typedef struct {
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string positive;
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string negative;
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} filter_expression_parts_t;
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function automatic array_of_string_t split_by_char(string c, string s);
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string parts[$];
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int last_char_position = -1;
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for (int i = 0; i < s.len(); i++) begin
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if (i == s.len()-1)
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parts.push_back(s.substr(last_char_position+1, i));
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if (string'(s[i]) == c) begin
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parts.push_back(s.substr(last_char_position+1, i-1));
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last_char_position = i;
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end
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end
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$display("%p", parts);
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return parts;
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endfunction
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function filter_expression_parts_t get_filter_expression_parts(string raw_filter);
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string parts[];
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parts = split_by_char("-", raw_filter);
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return '{ parts[0], parts[1] };
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endfunction
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initial begin
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string raw_filter = "parta-partb";
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filter_expression_parts_t parts = get_filter_expression_parts(raw_filter);
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$display("%p", parts);
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if (parts.positive != "parta") $stop;
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if (parts.negative != "partb") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -637,11 +637,9 @@
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<and loc="d,11,8,11,9" dtype_id="9">
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<and loc="d,11,8,11,9" dtype_id="9">
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<const loc="d,11,8,11,9" name="32'h1" dtype_id="14"/>
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<const loc="d,11,8,11,9" name="32'h1" dtype_id="14"/>
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<not loc="d,11,8,11,9" dtype_id="9">
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<not loc="d,11,8,11,9" dtype_id="9">
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<ccast loc="d,11,8,11,9" dtype_id="9">
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<cmethodhard loc="d,11,8,11,9" name="any" dtype_id="9">
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<cmethodhard loc="d,11,8,11,9" name="any" dtype_id="9">
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<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="9"/>
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<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="9"/>
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</cmethodhard>
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</cmethodhard>
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</ccast>
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</not>
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</not>
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</and>
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</and>
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<begin>
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<begin>
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@ -666,11 +664,9 @@
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<and loc="d,11,8,11,9" dtype_id="9">
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<and loc="d,11,8,11,9" dtype_id="9">
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<const loc="d,11,8,11,9" name="32'h1" dtype_id="14"/>
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<const loc="d,11,8,11,9" name="32'h1" dtype_id="14"/>
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<not loc="d,11,8,11,9" dtype_id="9">
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<not loc="d,11,8,11,9" dtype_id="9">
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<ccast loc="d,11,8,11,9" dtype_id="9">
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<cmethodhard loc="d,11,8,11,9" name="any" dtype_id="9">
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<cmethodhard loc="d,11,8,11,9" name="any" dtype_id="9">
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<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="9"/>
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<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="9"/>
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</cmethodhard>
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</cmethodhard>
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</ccast>
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</not>
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</not>
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</and>
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</and>
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<begin>
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<begin>
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