Fix intent error on quoted strings (#6544).
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@ -96,6 +96,7 @@ Verilator 5.041 devel
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* Fix inconsistent force assignment (#6541). [Artur Bieniek, Antmicro Ltd.]
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* Fix DFG circular driver tracing with partial assignments. [Geza Lore]
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* Fix passing typedef value as parameter (#6543). [Igor Zaworski, Antmicro Ltd.]
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* Fix intent error on quoted strings (#6544).
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Verilator 5.040 2025-08-30
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@ -794,29 +794,37 @@ void V3OutFormatter::putns(const AstNode* nodep, const char* strg) {
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}
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break;
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case '{':
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if (m_lang == LA_C && (equalsForBracket || m_bracketLevel)) {
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// Break up large code inside "= { ..."
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m_parenVec.push(m_indentLevel
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* m_blockIndent); // Line up continuation with block+1
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++m_bracketLevel;
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if (!m_inStringLiteral) {
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if (m_lang == LA_C && (equalsForBracket || m_bracketLevel)) {
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// Break up large code inside "= { ..."
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m_parenVec.push(m_indentLevel
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* m_blockIndent); // Line up continuation with block+1
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++m_bracketLevel;
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}
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indentInc();
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}
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indentInc();
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break;
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case '}':
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if (m_bracketLevel > 0) {
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m_parenVec.pop();
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--m_bracketLevel;
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if (!m_inStringLiteral) {
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if (m_bracketLevel > 0) {
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m_parenVec.pop();
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--m_bracketLevel;
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}
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indentDec();
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}
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indentDec();
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break;
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case '(':
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indentInc();
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// Line up continuation with open paren, plus one indent
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m_parenVec.push(m_column);
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if (!m_inStringLiteral) {
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indentInc();
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// Line up continuation with open paren, plus one indent
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m_parenVec.push(m_column);
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}
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break;
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case ')':
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if (!m_parenVec.empty()) m_parenVec.pop();
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indentDec();
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if (!m_inStringLiteral) {
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if (!m_parenVec.empty()) m_parenVec.pop();
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indentDec();
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}
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break;
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case '<':
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if (m_lang == LA_XML) {
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,44 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef int unsigned ahb_addr_t;
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typedef int unsigned ahb_data_t;
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class ahb_seq_item;
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ahb_addr_t address;
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ahb_data_t data[];
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function string to_string();
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string result_str, data_str;
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result_str = $sformatf(" addr=0x%0x ", address);
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data_str = " data=";
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if (data.size() == 0) data_str = {data_str, "-"};
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else if (data.size() == 1) data_str = {data_str, $sformatf("0x%0x", data[0])};
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else begin
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data_str = {data_str, $sformatf("%0d'{", data.size())};
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foreach (data[i]) data_str = {data_str, $sformatf(" 0x%0x", data[i])};
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data_str = {data_str, " }"};
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end
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result_str = {result_str, data_str};
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return result_str;
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endfunction
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endclass
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module top;
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initial begin
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ahb_seq_item tr;
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tr = new();
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tr.data = '{'h11, 'h22, 'h33, 'h44, 'h55, 'h66};
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$display(" tr(bytes, LE) @0x10: %0s", tr.to_string());
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$finish;
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end
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endmodule
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