Fix intent error on quoted strings (#6544).

This commit is contained in:
Wilson Snyder 2025-10-09 21:24:27 -04:00
parent 3306ed146b
commit 41b05cb1f8
4 changed files with 86 additions and 15 deletions

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@ -96,6 +96,7 @@ Verilator 5.041 devel
* Fix inconsistent force assignment (#6541). [Artur Bieniek, Antmicro Ltd.]
* Fix DFG circular driver tracing with partial assignments. [Geza Lore]
* Fix passing typedef value as parameter (#6543). [Igor Zaworski, Antmicro Ltd.]
* Fix intent error on quoted strings (#6544).
Verilator 5.040 2025-08-30

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@ -794,29 +794,37 @@ void V3OutFormatter::putns(const AstNode* nodep, const char* strg) {
}
break;
case '{':
if (m_lang == LA_C && (equalsForBracket || m_bracketLevel)) {
// Break up large code inside "= { ..."
m_parenVec.push(m_indentLevel
* m_blockIndent); // Line up continuation with block+1
++m_bracketLevel;
if (!m_inStringLiteral) {
if (m_lang == LA_C && (equalsForBracket || m_bracketLevel)) {
// Break up large code inside "= { ..."
m_parenVec.push(m_indentLevel
* m_blockIndent); // Line up continuation with block+1
++m_bracketLevel;
}
indentInc();
}
indentInc();
break;
case '}':
if (m_bracketLevel > 0) {
m_parenVec.pop();
--m_bracketLevel;
if (!m_inStringLiteral) {
if (m_bracketLevel > 0) {
m_parenVec.pop();
--m_bracketLevel;
}
indentDec();
}
indentDec();
break;
case '(':
indentInc();
// Line up continuation with open paren, plus one indent
m_parenVec.push(m_column);
if (!m_inStringLiteral) {
indentInc();
// Line up continuation with open paren, plus one indent
m_parenVec.push(m_column);
}
break;
case ')':
if (!m_parenVec.empty()) m_parenVec.pop();
indentDec();
if (!m_inStringLiteral) {
if (!m_parenVec.empty()) m_parenVec.pop();
indentDec();
}
break;
case '<':
if (m_lang == LA_XML) {

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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@ -0,0 +1,44 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef int unsigned ahb_addr_t;
typedef int unsigned ahb_data_t;
class ahb_seq_item;
ahb_addr_t address;
ahb_data_t data[];
function string to_string();
string result_str, data_str;
result_str = $sformatf(" addr=0x%0x ", address);
data_str = " data=";
if (data.size() == 0) data_str = {data_str, "-"};
else if (data.size() == 1) data_str = {data_str, $sformatf("0x%0x", data[0])};
else begin
data_str = {data_str, $sformatf("%0d'{", data.size())};
foreach (data[i]) data_str = {data_str, $sformatf(" 0x%0x", data[i])};
data_str = {data_str, " }"};
end
result_str = {result_str, data_str};
return result_str;
endfunction
endclass
module top;
initial begin
ahb_seq_item tr;
tr = new();
tr.data = '{'h11, 'h22, 'h33, 'h44, 'h55, 'h66};
$display(" tr(bytes, LE) @0x10: %0s", tr.to_string());
$finish;
end
endmodule