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Tests: Support ANSI input in driver

This commit is contained in:
Wilson Snyder 2025-09-13 08:53:23 -04:00
parent 1f61351e8f
commit 419e775dfb
2 changed files with 15 additions and 23 deletions
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5
test_regress/driver.py
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@ -2252,9 +2252,10 @@ class VlTest:
inputs = {} inputs = {}
for line in fh: for line in fh:
if get_sigs: if get_sigs:
m = re.match(r'^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;', line) # Does not support escaped signals, we only need "clk" and a few others
m = re.match(r'^\s*input\s*(logic|bit|reg|wire)?\s*([A-Za-z0-9_]+)', line)
if m: if m:
inputs[m.group(1)] = m.group(1) inputs[m.group(2)] = m.group(2)
if re.match(r'^\s*(function|task|endmodule)', line): if re.match(r'^\s*(function|task|endmodule)', line):
get_sigs = False get_sigs = False
# Ignore any earlier inputs; Module 't' has precedence # Ignore any earlier inputs; Module 't' has precedence

33
test_regress/t/t_EXAMPLE.v
View File

@ -22,22 +22,20 @@
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on // verilog_format: on
module t ( /*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
int cyc; int cyc;
reg [63:0] crc; logic [63:0] crc;
reg [63:0] sum; logic [63:0] sum;
// Take CRC data and apply to testblock inputs // Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0]; wire [31:0] in = crc[31:0];
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v logic [31:0] out; // From test of Test.v
// End of automatics // End of automatics
Test test ( /*AUTOINST*/ Test test ( /*AUTOINST*/
@ -66,8 +64,6 @@ module t ( /*AUTOARG*/
else if (cyc < 10) begin else if (cyc < 10) begin
sum <= '0; sum <= '0;
end end
else if (cyc < 90) begin
end
else if (cyc == 99) begin else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`checkh(crc, 64'hc77bb9b3784ea091); `checkh(crc, 64'hc77bb9b3784ea091);
@ -80,22 +76,17 @@ module t ( /*AUTOARG*/
endmodule endmodule
module Test ( /*AUTOARG*/ module Test (
// Outputs input clk,
out, input [31:0] in,
// Inputs output logic [31:0] out
clk, in );
);
// Replace this module with the device under test. // Replace this module with the device under test.
// //
// Change the code in the t module to apply values to the inputs and // Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector. // merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin always @(posedge clk) begin
out <= in; out <= in;
end end