Fix upcasting class type parameters (#6344)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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Krzysztof Bieganski 2025-08-30 03:20:09 +02:00 committed by GitHub
parent 91ae4c35b7
commit 40dda323fe
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3 changed files with 51 additions and 1 deletions

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@ -1337,7 +1337,8 @@ public:
} }
void visit(AstCCast* nodep) override { void visit(AstCCast* nodep) override {
// Extending a value of the same word width is just a NOP. // Extending a value of the same word width is just a NOP.
if (const AstClassRefDType* const classDtypep = VN_CAST(nodep->dtypep(), ClassRefDType)) { if (const AstClassRefDType* const classDtypep
= VN_CAST(nodep->dtypep()->skipRefp(), ClassRefDType)) {
putns(nodep, "(" + classDtypep->cType("", false, false) + ")("); putns(nodep, "(" + classDtypep->cType("", false, false) + ")(");
} else if (nodep->size() <= VL_BYTESIZE) { } else if (nodep->size() <= VL_BYTESIZE) {
putns(nodep, "(CData)("); putns(nodep, "(CData)(");

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.passes()

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@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
class factory #(type T);
static function T create;
T obj = new;
return obj;
endfunction
endclass
class foo;
endclass
class bar extends foo;
static function bar create;
bar b = new;
return b;
endfunction
endclass
module t;
initial begin
foo f;
if (bit'($random))
f = bar::create;
else
f = factory#(foo)::create();
$finish;
end
endmodule;