Support ##[*], ##[+], ##[M:$] unbounded cycle delays in SVA properties
This commit is contained in:
Yilou Wang
parent
e7a644a3fc
commit
3cc75be0a6
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@ -602,44 +602,68 @@ class RangeDelayExpander final : public VNVisitor {
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AstNodeExpr* exprp; // Expression to check (nullptr if unary leading delay)
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int delay; // Fixed delay after this expression (0 for tail)
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bool isRange; // Whether this step's delay is a range
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bool isUnbounded; // Whether the range is unbounded (rhs is AstUnbounded)
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int rangeMin;
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int rangeMax;
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int rangeMax; // -1 for unbounded
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};
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// Extract delay bounds from AstDelay. Clones and constifies (does not modify original AST).
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bool extractDelayBounds(AstDelay* dlyp, bool& isRange, int& minVal, int& maxVal) {
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// For unbounded ranges (rhs is AstUnbounded), maxVal is set to -1; rhsp is not constified.
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bool extractDelayBounds(AstDelay* dlyp, bool& isRange, bool& isUnbounded, int& minVal,
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int& maxVal) {
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isRange = dlyp->isRangeDelay();
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isUnbounded = dlyp->isUnbounded();
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AstNodeExpr* const minExprp = V3Const::constifyEdit(dlyp->lhsp()->cloneTree(false));
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const AstConst* const minConstp = VN_CAST(minExprp, Const);
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if (isRange) {
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AstNodeExpr* const maxExprp = V3Const::constifyEdit(dlyp->rhsp()->cloneTree(false));
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const AstConst* const maxConstp = VN_CAST(maxExprp, Const);
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if (!minConstp || !maxConstp) {
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dlyp->v3error("Range delay bounds must be elaboration-time constants"
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" (IEEE 1800-2023 16.7)");
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if (isUnbounded) {
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// ##[M:$], ##[*], ##[+]: only min bound; max is open-ended
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if (!minConstp) {
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dlyp->v3error("Range delay minimum must be an elaboration-time constant"
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" (IEEE 1800-2023 16.7)");
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VL_DO_DANGLING(minExprp->deleteTree(), minExprp);
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return false;
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}
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minVal = minConstp->toSInt();
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maxVal = -1;
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VL_DO_DANGLING(minExprp->deleteTree(), minExprp);
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if (minVal < 0) {
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dlyp->v3error("Range delay bounds must be non-negative"
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" (IEEE 1800-2023 16.7)");
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return false;
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}
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} else {
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AstNodeExpr* const maxExprp
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= V3Const::constifyEdit(dlyp->rhsp()->cloneTree(false));
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const AstConst* const maxConstp = VN_CAST(maxExprp, Const);
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if (!minConstp || !maxConstp) {
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dlyp->v3error("Range delay bounds must be elaboration-time constants"
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" (IEEE 1800-2023 16.7)");
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VL_DO_DANGLING(minExprp->deleteTree(), minExprp);
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VL_DO_DANGLING(maxExprp->deleteTree(), maxExprp);
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return false;
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}
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minVal = minConstp->toSInt();
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maxVal = maxConstp->toSInt();
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VL_DO_DANGLING(minExprp->deleteTree(), minExprp);
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VL_DO_DANGLING(maxExprp->deleteTree(), maxExprp);
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return false;
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}
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minVal = minConstp->toSInt();
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maxVal = maxConstp->toSInt();
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VL_DO_DANGLING(minExprp->deleteTree(), minExprp);
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VL_DO_DANGLING(maxExprp->deleteTree(), maxExprp);
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if (minVal < 0 || maxVal < 0) {
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dlyp->v3error("Range delay bounds must be non-negative"
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" (IEEE 1800-2023 16.7)");
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return false;
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}
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if (maxVal < minVal) {
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dlyp->v3error("Range delay maximum must be >= minimum"
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" (IEEE 1800-2023 16.7)");
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return false;
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}
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if (minVal == 0) {
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dlyp->v3warn(E_UNSUPPORTED, "Unsupported: ##0 in range delays");
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return false;
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if (minVal < 0 || maxVal < 0) {
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dlyp->v3error("Range delay bounds must be non-negative"
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" (IEEE 1800-2023 16.7)");
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return false;
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}
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if (maxVal < minVal) {
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dlyp->v3error("Range delay maximum must be >= minimum"
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" (IEEE 1800-2023 16.7)");
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return false;
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}
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if (minVal == 0) {
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dlyp->v3warn(E_UNSUPPORTED, "Unsupported: ##0 in bounded range delays");
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return false;
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}
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}
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} else {
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isUnbounded = false;
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minVal = maxVal = minConstp ? minConstp->toSInt() : 0;
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VL_DO_DANGLING(minExprp->deleteTree(), minExprp);
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}
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@ -663,127 +687,165 @@ class RangeDelayExpander final : public VNVisitor {
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AstDelay* const dlyp = VN_CAST(curp->delayp(), Delay);
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UASSERT_OBJ(dlyp, curp, "Expected AstDelay");
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bool isRange = false;
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bool isUnbounded = false;
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int minVal = 0;
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int maxVal = 0;
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if (!extractDelayBounds(dlyp, isRange, minVal, maxVal)) return false;
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if (!extractDelayBounds(dlyp, isRange, isUnbounded, minVal, maxVal)) return false;
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if (isRange) hasRange = true;
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if (curp->preExprp() && !VN_IS(curp->preExprp(), SExpr)) {
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steps.push_back({curp->preExprp(), minVal, isRange, minVal, maxVal});
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steps.push_back({curp->preExprp(), minVal, isRange, isUnbounded, minVal, maxVal});
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} else {
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steps.push_back({nullptr, minVal, isRange, minVal, maxVal});
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steps.push_back({nullptr, minVal, isRange, isUnbounded, minVal, maxVal});
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}
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if (AstSExpr* const nextp = VN_CAST(curp->exprp(), SExpr)) {
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return linearizeImpl(nextp, steps, hasRange);
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}
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steps.push_back({curp->exprp(), 0, false, 0, 0});
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steps.push_back({curp->exprp(), 0, false, false, 0, 0});
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return true;
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}
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// Build FSM body as if/else chain on state variable.
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// State 0 = IDLE. Each range delay adds 2 states (wait + check),
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// each fixed delay adds 1 (wait), each tail expr adds 1 (check).
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//
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// Example: a ##[M:N] b ##1 c
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// steps: [{a, range[M:N]}, {b, delay=1}, {c, delay=0}]
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// State 1: WAIT_MIN (count down M cycles)
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// State 2: CHECK_RANGE (check b each cycle, up to N-M retries)
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// State 3: WAIT_FIXED (count down 1 cycle for ##1)
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// State 4: CHECK_TAIL (check c, report pass/fail)
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AstNode* buildFsmBody(FileLine* flp, AstVar* stateVarp, AstVar* cntVarp, AstVar* failVarp,
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const std::vector<SeqStep>& steps, AstSenItem* /*sensesp*/,
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AstNodeExpr* antExprp) {
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// Pre-assigned state numbers for one SeqStep.
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// Range steps consume their successor (check target); successor entry is unused.
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struct StepBounds {
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int waitState; // WAIT_MIN state, or -1 if not needed
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int checkState; // CHECK or TAIL state; -1 for fixed-delay steps
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};
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// Assign state numbers to all steps before building FSM bodies.
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//
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// State layout for a ##[M:N] b ##1 c (bounded, M>0):
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// State 0: IDLE -- detect trigger, launch FSM
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// State 1: WAIT_MIN -- count down M-1 cycles
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// State 2: CHECK -- sample b; fail after N-M retries
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// State 3: WAIT_FIX -- count down 1 cycle for ##1
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// State 4: TAIL -- sample c, report pass/fail
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//
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// For ##[M:$] b ... (unbounded, M>1): same as bounded but CHECK has no timeout.
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// For ##[+] b (unbounded, M=1): WAIT_MIN skipped; CHECK is state 1.
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// For ##[*] b (unbounded, M=0): handled in IDLE directly (no WAIT_MIN).
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//
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// LIMITATION: single-evaluation FSM -- overlapping triggers are ignored
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// while the FSM is active. For ##[M:$], if the consequent never becomes
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// true the FSM remains in CHECK indefinitely, blocking new evaluations.
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std::vector<StepBounds> preAssignStates(const std::vector<SeqStep>& steps) {
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std::vector<StepBounds> bounds(steps.size(), {-1, -1});
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int s = 1;
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for (size_t i = 0; i < steps.size(); ++i) {
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const SeqStep& step = steps[i];
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if (step.isRange) {
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// Unbounded with min<=1: no WAIT_MIN (counter starts at 0 in CHECK).
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const bool needsWait = !step.isUnbounded || step.rangeMin > 1;
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if (needsWait) bounds[i].waitState = s++;
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bounds[i].checkState = s++;
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++i; // step[i+1] is the check target, not a separate FSM state
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} else if (step.delay > 0) {
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bounds[i].waitState = s++;
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} else {
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bounds[i].checkState = s++; // tail check
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}
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}
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return bounds;
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}
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// Build the match action for a range CHECK state.
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// isTail=true: return to IDLE; isTail=false: advance to afterMatchState.
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AstNode* makeOnMatchAction(FileLine* flp, AstVar* stateVarp, AstVar* cntVarp, bool isTail,
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int afterMatchState, int nextDelay) {
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if (isTail) {
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return new AstAssign{flp, new AstVarRef{flp, stateVarp, VAccess::WRITE},
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new AstConst{flp, 0}};
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}
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return makeStateTransition(flp, stateVarp, cntVarp, afterMatchState,
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nextDelay > 0 ? nextDelay - 1 : 0);
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}
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// Build the body of a range CHECK state.
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// Bounded: fail on timeout, decrement counter otherwise.
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// Unbounded: stay until match (no timeout).
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AstNode* makeRangeCheckBody(FileLine* flp, AstVar* stateVarp, AstVar* cntVarp,
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AstVar* failVarp, AstNodeExpr* exprp, AstNode* matchActionp,
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bool isUnbounded) {
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if (isUnbounded) {
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return new AstIf{flp, new AstSampled{flp, exprp->cloneTree(false)}, matchActionp,
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nullptr};
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}
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AstBegin* const timeoutp = new AstBegin{flp, "", nullptr, true};
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timeoutp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, failVarp, VAccess::WRITE},
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new AstConst{flp, AstConst::BitTrue{}}});
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timeoutp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, stateVarp, VAccess::WRITE},
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new AstConst{flp, 0}});
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AstNode* const decrementp = new AstAssign{
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flp, new AstVarRef{flp, cntVarp, VAccess::WRITE},
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new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 1}}};
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AstIf* const failOrRetryp = new AstIf{
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flp, new AstEq{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 0}},
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timeoutp, decrementp};
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return new AstIf{flp, new AstSampled{flp, exprp->cloneTree(false)}, matchActionp,
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failOrRetryp};
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}
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AstNode* buildFsmBody(FileLine* flp, AstVar* stateVarp, AstVar* cntVarp, AstVar* failVarp,
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const std::vector<SeqStep>& steps, AstNodeExpr* antExprp) {
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const std::vector<StepBounds> bounds = preAssignStates(steps);
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AstNode* fsmChainp = nullptr;
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int nextState = 1;
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for (size_t i = 0; i < steps.size(); ++i) {
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const SeqStep& step = steps[i];
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if (step.isRange) {
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// Range delay needs two states: WAIT_MIN and CHECK_RANGE
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UASSERT(i + 1 < steps.size(), "Range must have next step");
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const int waitState = nextState++;
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const int checkState = nextState++;
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const int rangeWidth = step.rangeMax - step.rangeMin;
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const SeqStep& nextStep = steps[i + 1];
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const int afterMatchState = bounds[i].checkState + 1;
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const bool isTail = (i + 2 >= steps.size() && nextStep.delay == 0);
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const int afterMatchState = nextState;
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// WAIT_MIN: count down rangeMin cycles
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{
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AstNode* const bodyp = new AstIf{
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// WAIT_MIN state: count down rangeMin-1 cycles before entering CHECK
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if (bounds[i].waitState >= 0) {
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const int initCnt
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= step.isUnbounded ? 0 : (step.rangeMax - step.rangeMin);
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AstNode* const waitBodyp = new AstIf{
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flp,
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new AstEq{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 0}},
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makeStateTransition(flp, stateVarp, cntVarp, checkState, rangeWidth),
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makeStateTransition(flp, stateVarp, cntVarp, bounds[i].checkState,
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initCnt),
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new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE},
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new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 1}}}};
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fsmChainp = chainState(flp, fsmChainp, stateVarp, waitState, bodyp);
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fsmChainp
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= chainState(flp, fsmChainp, stateVarp, bounds[i].waitState, waitBodyp);
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}
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// CHECK_RANGE: check expr each cycle, fail on timeout
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{
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AstNode* matchActionp = nullptr;
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AstNode* const timeoutp = new AstBegin{flp, "", nullptr, true};
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VN_AS(timeoutp, Begin)
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->addStmtsp(new AstAssign{flp,
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new AstVarRef{flp, failVarp, VAccess::WRITE},
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new AstConst{flp, AstConst::BitTrue{}}});
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VN_AS(timeoutp, Begin)
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->addStmtsp(new AstAssign{flp,
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new AstVarRef{flp, stateVarp, VAccess::WRITE},
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new AstConst{flp, 0}});
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AstNode* const decrementp
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= new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE},
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new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 1}}};
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// CHECK state: sample consequent each cycle
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AstNode* const matchActionp = makeOnMatchAction(flp, stateVarp, cntVarp, isTail,
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afterMatchState, nextStep.delay);
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AstNode* const checkBodyp
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= makeRangeCheckBody(flp, stateVarp, cntVarp, failVarp, nextStep.exprp,
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matchActionp, step.isUnbounded);
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fsmChainp
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= chainState(flp, fsmChainp, stateVarp, bounds[i].checkState, checkBodyp);
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AstIf* const failOrRetryp
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= new AstIf{flp,
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new AstEq{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 0}},
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timeoutp, decrementp};
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if (nextStep.delay > 0) {
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matchActionp = makeStateTransition(flp, stateVarp, cntVarp,
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afterMatchState, nextStep.delay - 1);
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} else {
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matchActionp
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= makeStateTransition(flp, stateVarp, cntVarp, afterMatchState, 0);
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}
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AstIf* const checkp
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= new AstIf{flp, new AstSampled{flp, nextStep.exprp->cloneTree(false)},
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matchActionp, failOrRetryp};
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fsmChainp = chainState(flp, fsmChainp, stateVarp, checkState, checkp);
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}
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// Skip next step (already consumed as the range check target)
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++i;
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++i; // step[i+1] consumed as the CHECK target
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continue;
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} else if (step.delay > 0) {
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// Fixed delay: count down then advance
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const int waitState = nextState++;
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// Fixed delay: count down then advance to next state
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const int nextStateNum = bounds[i].waitState + 1;
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AstNode* const bodyp = new AstIf{
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flp,
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new AstEq{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 0}},
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new AstAssign{flp, new AstVarRef{flp, stateVarp, VAccess::WRITE},
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new AstConst{flp, static_cast<uint32_t>(nextState)}},
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new AstConst{flp, static_cast<uint32_t>(nextStateNum)}},
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new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE},
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new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 1}}}};
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fsmChainp = chainState(flp, fsmChainp, stateVarp, waitState, bodyp);
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fsmChainp = chainState(flp, fsmChainp, stateVarp, bounds[i].waitState, bodyp);
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} else if (i == steps.size() - 1 && step.exprp) {
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// Tail: check final expression, pass or fail
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const int checkState = nextState++;
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// Tail: sample final expression, report pass/fail
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AstNode* const passp = new AstAssign{
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flp, new AstVarRef{flp, stateVarp, VAccess::WRITE}, new AstConst{flp, 0}};
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AstBegin* const failp = new AstBegin{flp, "", nullptr, true};
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@ -791,27 +853,17 @@ class RangeDelayExpander final : public VNVisitor {
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new AstConst{flp, AstConst::BitTrue{}}});
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failp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, stateVarp, VAccess::WRITE},
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new AstConst{flp, 0}});
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AstIf* const bodyp = new AstIf{
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flp, new AstSampled{flp, step.exprp->cloneTree(false)}, passp, failp};
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fsmChainp = chainState(flp, fsmChainp, stateVarp, checkState, bodyp);
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fsmChainp = chainState(flp, fsmChainp, stateVarp, bounds[i].checkState, bodyp);
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}
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}
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// Build IDLE state (state 0): check trigger and start
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// Build IDLE state (state 0)
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AstNode* idleBodyp = nullptr;
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const SeqStep& firstStep = steps[0];
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int initCnt = 0;
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if (firstStep.isRange) {
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initCnt = firstStep.rangeMin - 1;
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} else {
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initCnt = firstStep.delay - 1;
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}
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AstNode* const startActionp
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= makeStateTransition(flp, stateVarp, cntVarp, 1, initCnt < 0 ? 0 : initCnt);
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// Trigger = antecedent (from implication) AND/OR first step expression
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// Trigger = antecedent AND/OR first step expression
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AstNodeExpr* triggerp = nullptr;
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if (antExprp && firstStep.exprp) {
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triggerp = new AstAnd{flp, new AstSampled{flp, antExprp->cloneTree(false)},
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@ -822,12 +874,37 @@ class RangeDelayExpander final : public VNVisitor {
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triggerp = new AstSampled{flp, firstStep.exprp->cloneTree(false)};
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}
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if (triggerp) {
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triggerp->dtypeSetBit();
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idleBodyp = new AstIf{flp, triggerp, startActionp, nullptr};
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if (firstStep.isUnbounded && firstStep.rangeMin == 0 && steps.size() > 1) {
|
||||
// ##[*] / ##[0:$]: check consequent immediately in IDLE.
|
||||
// On ##0 match: perform match action without entering CHECK.
|
||||
// On no match: enter CHECK (state bounds[0].checkState) to wait.
|
||||
const SeqStep& nextStep = steps[1];
|
||||
const int checkState = bounds[0].checkState;
|
||||
const int afterMatch = checkState + 1;
|
||||
const bool isTail = (steps.size() == 2 && nextStep.delay == 0);
|
||||
AstNodeExpr* const immCheckp = new AstSampled{flp, nextStep.exprp->cloneTree(false)};
|
||||
immCheckp->dtypeSetBit();
|
||||
AstNode* const immMatchp
|
||||
= makeOnMatchAction(flp, stateVarp, cntVarp, isTail, afterMatch, nextStep.delay);
|
||||
AstNode* const toCheckp = makeStateTransition(flp, stateVarp, cntVarp, checkState, 0);
|
||||
AstIf* const starBodyp = new AstIf{flp, immCheckp, immMatchp, toCheckp};
|
||||
if (triggerp) {
|
||||
triggerp->dtypeSetBit();
|
||||
idleBodyp = new AstIf{flp, triggerp, starBodyp, nullptr};
|
||||
} else {
|
||||
idleBodyp = starBodyp;
|
||||
}
|
||||
} else {
|
||||
// Unary form with no antecedent: start unconditionally each cycle
|
||||
idleBodyp = startActionp;
|
||||
// Standard start: transition to state 1 with appropriate counter
|
||||
int initCnt = firstStep.isRange ? firstStep.rangeMin - 1 : firstStep.delay - 1;
|
||||
AstNode* const startActionp
|
||||
= makeStateTransition(flp, stateVarp, cntVarp, 1, initCnt < 0 ? 0 : initCnt);
|
||||
if (triggerp) {
|
||||
triggerp->dtypeSetBit();
|
||||
idleBodyp = new AstIf{flp, triggerp, startActionp, nullptr};
|
||||
} else {
|
||||
idleBodyp = startActionp;
|
||||
}
|
||||
}
|
||||
|
||||
// Chain: if (state == 0) idle else if (state == 1) ... else ...
|
||||
|
|
@ -940,16 +1017,19 @@ class RangeDelayExpander final : public VNVisitor {
|
|||
AstVar* const stateVarp = new AstVar{flp, VVarType::MODULETEMP, baseName + "__state",
|
||||
nodep->findBasicDType(VBasicDTypeKwd::UINT32)};
|
||||
stateVarp->lifetime(VLifetime::STATIC_EXPLICIT);
|
||||
stateVarp->noSample(true);
|
||||
AstVar* const cntVarp = new AstVar{flp, VVarType::MODULETEMP, baseName + "__cnt",
|
||||
nodep->findBasicDType(VBasicDTypeKwd::UINT32)};
|
||||
cntVarp->lifetime(VLifetime::STATIC_EXPLICIT);
|
||||
cntVarp->noSample(true);
|
||||
AstVar* const failVarp = new AstVar{flp, VVarType::MODULETEMP, baseName + "__fail",
|
||||
nodep->findBasicDType(VBasicDTypeKwd::BIT)};
|
||||
failVarp->lifetime(VLifetime::STATIC_EXPLICIT);
|
||||
failVarp->noSample(true);
|
||||
|
||||
// Build FSM body
|
||||
AstNode* const fsmBodyp
|
||||
= buildFsmBody(flp, stateVarp, cntVarp, failVarp, steps, sensesp, antExprp);
|
||||
= buildFsmBody(flp, stateVarp, cntVarp, failVarp, steps, antExprp);
|
||||
|
||||
// Create Always block for the FSM (same scheduling as assertion always blocks)
|
||||
AstAlways* const alwaysp = new AstAlways{
|
||||
|
|
|
|||
|
|
@ -562,6 +562,7 @@ public:
|
|||
VTimescale timeunit() const { return m_timeunit; }
|
||||
bool isCycleDelay() const { return m_isCycle; }
|
||||
bool isRangeDelay() const { return rhsp() != nullptr; }
|
||||
bool isUnbounded() const { return rhsp() && VN_IS(rhsp(), Unbounded); }
|
||||
};
|
||||
class AstDisable final : public AstNodeStmt {
|
||||
// @astgen op1 := targetRefp : Optional[AstNodeExpr] // Reference to link in V3LinkDot
|
||||
|
|
|
|||
|
|
@ -6885,11 +6885,11 @@ cycle_delay_range<delayp>: // IEEE: ==cycle_delay_range
|
|||
{ $$ = new AstDelay{$1, $3, true};
|
||||
$$->rhsp($5); }
|
||||
| yP_POUNDPOUND yP_BRASTAR ']'
|
||||
{ $$ = new AstDelay{$1, new AstConst{$1, AstConst::BitFalse{}}, true};
|
||||
BBUNSUP($<fl>1, "Unsupported: ## [*] cycle delay range expression"); }
|
||||
{ $$ = new AstDelay{$1, new AstConst{$1, 0}, true};
|
||||
$$->rhsp(new AstUnbounded{$1}); }
|
||||
| yP_POUNDPOUND yP_BRAPLUSKET
|
||||
{ $$ = new AstDelay{$1, new AstConst{$1, AstConst::BitFalse{}}, true};
|
||||
BBUNSUP($<fl>1, "Unsupported: ## [+] cycle delay range expression"); }
|
||||
{ $$ = new AstDelay{$1, new AstConst{$1, 1}, true};
|
||||
$$->rhsp(new AstUnbounded{$1}); }
|
||||
;
|
||||
|
||||
sequence_match_itemList<nodep>: // IEEE: [sequence_match_item] part of sequence_expr
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of either the GNU Lesser General Public License Version 3
|
||||
# or the Perl Artistic License Version 2.0.
|
||||
# SPDX-FileCopyrightText: 2026 Wilson Snyder
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing'])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain.
|
||||
// SPDX-FileCopyrightText: 2026 PlanV GmbH
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
module t (
|
||||
input clk
|
||||
);
|
||||
integer cyc = 0;
|
||||
reg [63:0] crc = '0;
|
||||
reg [63:0] sum = '0;
|
||||
|
||||
// Derive test signals from CRC
|
||||
wire a = crc[0];
|
||||
wire b = crc[1];
|
||||
wire c = crc[2];
|
||||
|
||||
wire [63:0] result = {61'h0, c, b, a};
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b\n", $time, cyc, crc, a, b, c);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||
|
||||
if (cyc == 0) begin
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc < 10) begin
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc == 99) begin
|
||||
`checkh(crc, 64'hc77bb9b3784ea091);
|
||||
`checkh(sum, 64'h38c614665c6b71ad);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
// ##[+] with always-true consequent (wait >= 1 cycle, then check 1'b1)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[+] 1'b1);
|
||||
|
||||
// ##[*] with always-true consequent (wait >= 0 cycles, then check 1'b1)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[*] 1'b1);
|
||||
|
||||
// ##[2:$] unbounded with min > 1
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
b |-> ##[2:$] 1'b1);
|
||||
|
||||
// ##[1:$] explicit unbounded (equivalent to ##[+])
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[1:$] 1'b1);
|
||||
|
||||
// Unary ##[+] without antecedent
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
##[+] 1'b1);
|
||||
|
||||
// Unary ##[*] without antecedent
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
##[*] 1'b1);
|
||||
|
||||
// Multi-step: ##[+] then ##1 (tests afterMatchState jump)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[+] 1'b1 ##1 1'b1);
|
||||
|
||||
// Multi-step: ##[*] then ##1 (tests ##[*] immediate match + continuation)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[*] 1'b1 ##1 1'b1);
|
||||
|
||||
// Multi-step: ##[3:$] then ##2 (larger min + continuation)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
b |-> ##[3:$] 1'b1 ##2 1'b1);
|
||||
|
||||
// Binary form without implication: a ##[+] b (no antecedent path)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a ##[+] 1'b1);
|
||||
|
||||
// Binary form without implication: a ##[*] b (no antecedent path)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a ##[*] 1'b1);
|
||||
|
||||
// Large min: ##[5:$] (multi-cycle WAIT_MIN countdown)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[5:$] 1'b1);
|
||||
|
||||
// --- Non-trivial consequents: exercise CHECK "stay" path ---
|
||||
|
||||
// ##[+] with CRC signal: wait 1+ cycles for b (exercises match-or-stay)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[+] b);
|
||||
|
||||
// ##[*] with CRC signal: immediate or deferred match of c
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a |-> ##[*] c);
|
||||
|
||||
// ##[2:$] with CRC signal: min wait then check b (WAIT_MIN + CHECK unbounded)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
b |-> ##[2:$] a);
|
||||
|
||||
// Binary form with CRC signal: a ##[+] b (no implication)
|
||||
assert property (@(posedge clk) disable iff (cyc < 2)
|
||||
a ##[+] b);
|
||||
|
||||
endmodule
|
||||
|
|
@ -11,9 +11,13 @@
|
|||
: ... note: In instance 't'
|
||||
24 | a3: assert property (@(posedge clk) a |-> ##[5:2] b);
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_property_sexpr_range_delay_bad.v:27:45: Unsupported: ##0 in range delays
|
||||
%Error-UNSUPPORTED: t/t_property_sexpr_range_delay_bad.v:27:45: Unsupported: ##0 in bounded range delays
|
||||
: ... note: In instance 't'
|
||||
27 | a4: assert property (@(posedge clk) a |-> ##[0:3] b);
|
||||
| ^~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error: t/t_property_sexpr_range_delay_bad.v:30:45: Range delay minimum must be an elaboration-time constant (IEEE 1800-2023 16.7)
|
||||
: ... note: In instance 't'
|
||||
30 | a5: assert property (@(posedge clk) a |-> ##[cyc:$] b);
|
||||
| ^~
|
||||
%Error: Exiting due to
|
||||
|
|
|
|||
|
|
@ -26,4 +26,7 @@ module t;
|
|||
// ##0 in range
|
||||
a4: assert property (@(posedge clk) a |-> ##[0:3] b);
|
||||
|
||||
// Non-constant minimum in unbounded range
|
||||
a5: assert property (@(posedge clk) a |-> ##[cyc:$] b);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -8,18 +8,6 @@
|
|||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:50:7: Unsupported: intersect (in sequence expression)
|
||||
50 | a intersect b;
|
||||
| ^~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:63:5: Unsupported: ## [*] cycle delay range expression
|
||||
63 | ## [*] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:66:5: Unsupported: ## [+] cycle delay range expression
|
||||
66 | ## [+] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:79:7: Unsupported: ## [*] cycle delay range expression
|
||||
79 | a ## [*] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:82:7: Unsupported: ## [+] cycle delay range expression
|
||||
82 | a ## [+] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: [*] boolean abbrev expression
|
||||
89 | a [*];
|
||||
| ^~
|
||||
|
|
|
|||
Loading…
Reference in New Issue