Fix conditional expression with parameterized classes (#8039)
Signed-off-by: Pawel Klopotek <pklopotek@internships.antmicro.com>
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@ -1735,12 +1735,15 @@ AstNodeDType* AstNode::getCommonClassTypep(AstNode* node1p, AstNode* node2p) {
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if (castable == VCastable::DYNAMIC_CLASS) return node2p->dtypep();
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if (castable == VCastable::DYNAMIC_CLASS) return node2p->dtypep();
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}
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}
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AstClassRefDType* classDtypep1 = VN_CAST(node1p->dtypep(), ClassRefDType);
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AstClassRefDType* classDtypep1 = VN_CAST(node1p->dtypep()->skipRefp(), ClassRefDType);
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while (classDtypep1) {
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while (classDtypep1) {
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const VCastable castable = computeCastable(classDtypep1, node2p->dtypep(), node2p);
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const VCastable castable = computeCastable(classDtypep1, node2p->dtypep(), node2p);
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if (castable == VCastable::COMPATIBLE) return classDtypep1;
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if (castable == VCastable::COMPATIBLE) return classDtypep1;
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const AstClassExtends* const extendsp = classDtypep1->classp()->extendsp();
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AstClassExtends* const extendsp = classDtypep1->classp()->extendsp();
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classDtypep1 = extendsp ? VN_AS(extendsp->dtypep(), ClassRefDType) : nullptr;
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if (!extendsp) break;
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AstNodeDType* const edtp
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= extendsp->dtypep() ? extendsp->dtypep() : extendsp->childDTypep();
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classDtypep1 = VN_AS(edtp->skipRefp(), ClassRefDType);
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}
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}
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return nullptr;
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return nullptr;
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}
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}
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,49 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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int value;
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endclass
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typedef Base Base_t;
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class SubA #(type T = int) extends Base_t;
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endclass
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class SubB #(type T = int) extends Base_t;
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endclass
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typedef SubA #(int) SubAInt_t;
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typedef SubB #(int) SubBInt_t;
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class Container;
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local SubAInt_t a;
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local SubBInt_t b;
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function new();
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a = new;
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a.value = 1;
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b = new;
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b.value = 2;
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endfunction
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function Base test(int sel);
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test = sel[0] ? a : b;
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endfunction
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endclass
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module t;
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Container c;
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int cyc;
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Base result;
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initial begin
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c = new;
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for (cyc = 0; cyc < 100; ++cyc) begin
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result = c.test(cyc);
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if (result.value != (cyc[0] ? 1 : 2)) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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