mirror of
https://github.com/verilator/verilator.git
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+5
-1
@@ -201,6 +201,7 @@ class GateBuildVisitor final : public VNVisitorConst {
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bool m_inClockedActive = false; // Underneath clocked active
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bool m_inEdgeActive = false; // Underneath edge active
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bool m_inStaticActive = false; // Underneath static active
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bool m_inInitialActive = false; // Underneath initial active
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bool m_inSenItem = false; // Underneath AstSenItem; any varrefs are clocks
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// METHODS
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@@ -224,7 +225,8 @@ class GateBuildVisitor final : public VNVisitorConst {
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m_logicVertexp->clearReducibleAndDedupable(nonReducibleReason);
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} else if (m_inClockedActive) {
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m_logicVertexp->clearReducible("Clocked logic"); // but dedupable
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} else if (m_inStaticActive) {
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} else if (m_inStaticActive || m_inInitialActive) {
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// Runs only once, so its output must not be treated as live combinational logic
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m_logicVertexp->setStaticInit();
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}
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if (consumeReason) m_logicVertexp->setConsumed(consumeReason);
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@@ -251,10 +253,12 @@ class GateBuildVisitor final : public VNVisitorConst {
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VL_RESTORER(m_inClockedActive);
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VL_RESTORER(m_inEdgeActive);
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VL_RESTORER(m_inStaticActive);
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VL_RESTORER(m_inInitialActive);
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m_activep = nodep;
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m_inClockedActive = nodep->hasClocked();
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m_inEdgeActive = nodep->sentreep() && nodep->sentreep()->hasEdge();
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m_inStaticActive = nodep->hasStatic();
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m_inInitialActive = nodep->hasInitial();
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// AstVarScope::user2 -> bool: Signal used in SenItem in *this* active block
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const VNUser2InUse user2InUse;
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