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https://github.com/verilator/verilator.git
synced 2026-10-06 01:54:01 +02:00
Internals: Remove dead NEW_ORDERING code.
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@@ -786,9 +786,7 @@ class EmitCImp : EmitCStmts {
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if (nodep->stmtsp()) puts("// Body\n");
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nodep->stmtsp()->iterateAndNext(*this);
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#ifndef NEW_ORDERING
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if (!m_blkChangeDetVec.empty()) emitChangeDet();
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#endif
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if (nodep->finalsp()) puts("// Final\n");
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nodep->finalsp()->iterateAndNext(*this);
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@@ -1621,20 +1619,16 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
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}
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puts("// Evaluate till stable\n");
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puts("VL_DEBUG_IF(VL_PRINTF(\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
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#ifndef NEW_ORDERING
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puts("int __VclockLoop = 0;\n");
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puts("IData __Vchange=1;\n");
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puts("while (VL_LIKELY(__Vchange)) {\n");
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puts( "VL_DEBUG_IF(VL_PRINTF(\" Clock loop\\n\"););\n");
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#endif
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puts( "vlSymsp->__Vm_activity = true;\n");
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puts( "_eval(vlSymsp);\n");
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#ifndef NEW_ORDERING
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puts( "__Vchange = _change_request(vlSymsp);\n");
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puts( "if (++__VclockLoop > "+cvtToStr(v3Global.opt.convergeLimit())
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+") vl_fatal(__FILE__,__LINE__,__FILE__,\"Verilated model didn't converge\");\n");
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puts("}\n");
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#endif
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puts("}\n");
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splitSizeInc(10);
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@@ -1642,20 +1636,16 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
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puts("\nvoid "+modClassName(modp)+"::_eval_initial_loop("+EmitCBaseVisitor::symClassVar()+") {\n");
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puts("vlSymsp->__Vm_didInit = true;\n");
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puts("_eval_initial(vlSymsp);\n");
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#ifndef NEW_ORDERING
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puts( "vlSymsp->__Vm_activity = true;\n");
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puts( "int __VclockLoop = 0;\n");
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puts( "IData __Vchange=1;\n");
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puts( "while (VL_LIKELY(__Vchange)) {\n");
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#endif
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puts( "_eval_settle(vlSymsp);\n");
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puts( "_eval(vlSymsp);\n");
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#ifndef NEW_ORDERING
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puts( "__Vchange = _change_request(vlSymsp);\n");
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puts( "if (++__VclockLoop > "+cvtToStr(v3Global.opt.convergeLimit())
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+") vl_fatal(__FILE__,__LINE__,__FILE__,\"Verilated model didn't DC converge\");\n");
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puts( "}\n");
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#endif
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puts("}\n");
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splitSizeInc(10);
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}
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