Tests: Auto detect and exit --timing with no coroutines

test_regress/driver.pl

@@ -153,6 +153,9 @@ if ($#opt_tests < 0) {  # Run everything
 @opt_tests = _calc_hashset(@opt_tests) if $opt_hashset;
 
 if ($#opt_tests >= 2 && $opt_jobs >= 2) {
+    # Read supported into master process, so don't call every subprocess
+    _have_coroutines();
+    _have_sc();
     # Without this tests such as t_debug_sigsegv_bt_bad.pl will occasionally
     # block on input and cause a SIGSTOP, then a "fg" was needed to resume testing.
     if (!$::Have_Forker) {
@@ -289,6 +292,35 @@ sub _calc_hashset {
     return @new;
 }
 
+#######################################################################
+# Verilator utilities
+
+our %_Verilator_Supported;
+sub _verilator_get_supported {
+    my $feature = shift;
+    # Returns if given feature is supported
+    if (!defined $_Verilator_Supported{$feature}) {
+        my @args = ("perl", "$ENV{VERILATOR_ROOT}/bin/verilator", "-get-supported", $feature);
+        my $args = join(' ', @args);
+        my $out = `$args`;
+        $out or die "couldn't run: $! " . join(' ', @args);
+        chomp $out;
+        $_Verilator_Supported{$feature} = ($out =~ /1/ ? 1 : 0);
+    }
+    return $_Verilator_Supported{$feature};
+}
+
+sub _have_coroutines {
+    return 1 if _verilator_get_supported('COROUTINES');
+    return 0;
+}
+
+sub _have_sc {
+    return 1 if (defined $ENV{SYSTEMC} || defined $ENV{SYSTEMC_INCLUDE} || $ENV{CFG_HAVE_SYSTEMC});
+    return 1 if _verilator_get_supported('SYSTEMC');
+    return 0;
+}
+
 #######################################################################
 #######################################################################
 #######################################################################
@@ -889,21 +921,22 @@ sub compile_vlt_flags {
     my %param = (%{$self}, @_);  # Default arguments are from $self
     return 1 if $self->errors || $self->skips;
 
-    my $checkflags = join(' ', @{$param{v_flags}},
+    my $checkflags = ' '.join(' ', @{$param{v_flags}},
-                          @{$param{v_flags2}},
+                              @{$param{v_flags2}},
-                          @{$param{verilator_flags}},
+                              @{$param{verilator_flags}},
-                          @{$param{verilator_flags2}},
+                              @{$param{verilator_flags2}},
-                          @{$param{verilator_flags3}});
+                              @{$param{verilator_flags3}});
     die "%Error: specify threads via 'threads =>' argument, not as a command line option" unless ($checkflags !~ /(^|\s)-?-threads\s/);
+    $self->{coverage} = 1 if ($checkflags =~ /-coverage\b/);
+    $self->{savable} = 1 if ($checkflags =~ /-savable\b/);
     $self->{sc} = 1 if ($checkflags =~ /-sc\b/);
+    $self->{timing} = 1 if ($checkflags =~ /\b-?-timing\b/ || $checkflags =~ /\b-?-binary\b/ );
     $self->{trace} = ($opt_trace || $checkflags =~ /-trace\b/
                       || $checkflags =~ /-trace-fst\b/);
     $self->{trace_format} = (($checkflags =~ /-trace-fst/ && $self->{sc} && 'fst-sc')
                              || ($checkflags =~ /-trace-fst/ && !$self->{sc} && 'fst-c')
                              || ($self->{sc} && 'vcd-sc')
                              || (!$self->{sc} && 'vcd-c'));
-    $self->{savable} = 1 if ($checkflags =~ /-savable\b/);
-    $self->{coverage} = 1 if ($checkflags =~ /-coverage\b/);
     $self->{sanitize} = $opt_sanitize unless exists($self->{sanitize});
     $self->{benchmarksim} = 1 if ($param{benchmarksim});
 
@@ -1113,7 +1146,10 @@ sub compile {
             $self->skip("Test requires SystemC; ignore error since not installed\n");
             return 1;
         }
-
+        if ($self->{timing} && !$self->have_coroutines) {
+            $self->skip("Test requires Coroutines; ignore error since not available\n");
+            return 1;
+        }
         if ($param{verilator_make_cmake} && !$self->have_cmake) {
             $self->skip("Test requires CMake; ignore error since not available or version too old\n");
             return 1;
@@ -1464,16 +1500,11 @@ sub sc {
 }
 
 sub have_sc {
-    my $self = (ref $_[0] ? shift : $Self);
+    return ::_have_sc();
-    return 1 if (defined $ENV{SYSTEMC} || defined $ENV{SYSTEMC_INCLUDE} || $ENV{CFG_HAVE_SYSTEMC});
-    return 1 if $self->verilator_get_supported('SYSTEMC');
-    return 0;
 }
 
 sub have_coroutines {
-    my $self = (ref $_[0] ? shift : $Self);
+    return ::_have_coroutines();
-    return 1 if $self->verilator_get_supported('COROUTINES');
-    return 0;
 }
 
 sub make_version {
@@ -2155,25 +2186,6 @@ sub _read_inputs_vhdl {
     $fh->close();
 }
 
-#######################################################################
-# Verilator utilities
-
-our %_Verilator_Supported;
-sub verilator_get_supported {
-    my $self = (ref $_[0] ? shift : $Self);
-    my $feature = shift;
-    # Returns if given feature is supported
-    if (!defined $_Verilator_Supported{$feature}) {
-        my @args = ("perl", "$ENV{VERILATOR_ROOT}/bin/verilator", "-get-supported", $feature);
-        my $args = join(' ', @args);
-        my $out = `$args`;
-        $out or die "couldn't run: $! " . join(' ', @args);
-        chomp $out;
-        $_Verilator_Supported{$feature} = ($out =~ /1/ ? 1 : 0);
-    }
-    return $_Verilator_Supported{$feature};
-}
-
 #######################################################################
 # File utilities
 

test_regress/t/t_clocking_sched_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,22 +10,17 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_clocking_sched.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_clocking_sched.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ["--timing"],
+    verilator_flags2 => ["--timing"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename}
+    expect_filename => $Self->{golden_filename}
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_clocking_timing1.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_clocking_timing.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_clocking_timing.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing"],
+    verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_clocking_timing2.pl

@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_clocking_timing.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_clocking_timing.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"],
+    verilator_flags2 => ["--exe --main --timing -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_cxx_equal_to.pl

@@ -10,23 +10,18 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_cxx_equal_to.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_cxx_equal_to.v");
 
-    compile(
+compile(
-        verilator_flags2 => ['--binary --timing --trace'],
+    verilator_flags2 => ['--exe --main --timing --timing --trace'],
-        verilator_make_cmake => 0,
+    verilator_make_cmake => 0,
-        verilator_make_gmake => 0,
+    verilator_make_gmake => 0,
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_delay_incr_timing.pl

@@ -12,21 +12,16 @@ scenarios(simulator => 1);
 
 $Self->{main_time_multiplier} = 10e-7 / 10e-9;
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_delay_incr.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_delay_incr.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ['--timing -Wno-ZERODLY'],
+    verilator_flags2 => ['--timing -Wno-ZERODLY'],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_delay_timing.pl

@@ -12,21 +12,16 @@ scenarios(simulator => 1);
 
 $Self->{main_time_multiplier} = 10e-7 / 10e-9;
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_delay.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_delay.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ['--timing -Wno-ZERODLY'],
+    verilator_flags2 => ['--timing -Wno-ZERODLY'],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_delay_var.pl

@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    fails => $Self->{vlt},
-    compile(
+    expect_filename => $Self->{golden_filename},
-        verilator_flags2 => ["--exe --main --timing"],
+    );
-        make_main => 0,
-        fails => $Self->{vlt},
-        expect_filename => $Self->{golden_filename},
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        ) if !$Self->{vlt};
+    ) if !$Self->{vlt};
-}
 
 ok(1);
 1;

test_regress/t/t_event_control_timing.pl

@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_event_control.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_event_control.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--timing"],
+    verilator_flags2 => ["--timing"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_flag_binary.pl

@@ -12,24 +12,19 @@ scenarios(simulator => 1);
 
 top_filename("t/t_flag_main.v");
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags => [# Custom as don't want -cc
-}
+                        "-Mdir $Self->{obj_dir}",
-else {
+                        "--debug-check", ],
-    compile(
+    verilator_flags2 => ['--binary'],
-        verilator_flags => [# Custom as don't want -cc
+    verilator_make_cmake => 0,
-                            "-Mdir $Self->{obj_dir}",
+    verilator_make_gmake => 0,
-                            "--debug-check", ],
+    make_main => 0,
-        verilator_flags2 => ['--binary'],
+    );
-        verilator_make_cmake => 0,
-        verilator_make_gmake => 0,
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_fork_label_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_fork_label.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_fork_label.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing"],
+    verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_fork_timing.pl

@@ -10,20 +10,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_fork.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_fork.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--timing"],
+    verilator_flags2 => ["--timing"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_func_lib_sub_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,16 +10,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);  # UNOPTTHREADS in vltmt
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_func_lib_sub.v");
-    skip("No coroutine support");
+
-}
+compile(
-else {
+    verilator_flags2 => ["--timing"],
-    top_filename("t/t_func_lib_sub.v");
+    );
 
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
-}
 # No execute
 ok(1);
 1;

test_regress/t/t_gate_basic_timing.pl

@@ -12,21 +12,16 @@ scenarios(simulator => 1);
 
 $Self->{main_time_multiplier} = 10e-7 / 10e-9;
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_gate_basic.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_gate_basic.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY"],
+    verilator_flags2 => ["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_mailbox.pl

@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing -Wall"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing -Wall"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_mailbox_class.pl

@@ -10,14 +10,9 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
-}
 
 ok(1);
 1;

test_regress/t/t_mailbox_std.pl

@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_mailbox.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_mailbox.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing -Wall --Wpedantic -DMAILBOX_T=std::mailbox"],
+    verilator_flags2 => ["--exe --main --timing -Wall --Wpedantic -DMAILBOX_T=std::mailbox"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_math_signed5_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_math_signed5.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_math_signed5.v");
 
-    compile(
+compile(
-        verilator_flags2 => ['--timing'],
+    verilator_flags2 => ['--timing'],
-        timing_loop => 1,
+    timing_loop => 1,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_net_delay_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_net_delay.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_net_delay.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ["--timing"],
+    verilator_flags2 => ["--timing"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_net_delay_timing_sc.pl

@@ -12,23 +12,15 @@ scenarios(simulator => 1);
 
 $Self->{main_time_multiplier} = 2;
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_net_delay.v");
-    skip("No coroutine support");
-}
-elsif (!$Self->have_sc) {
-    skip("No SystemC installed");
-}
-else {
-    top_filename("t/t_net_delay.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"],
+    verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_order_timing.pl

@@ -12,21 +12,16 @@ scenarios(simulator => 1);
 
 $Self->{main_time_multiplier} = 1e-8 / 1e-9;
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_order.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_order.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ["--timescale 10ns/1ns --timing"],
+    verilator_flags2 => ["--timescale 10ns/1ns --timing"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_package_ddecl_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_package_ddecl.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_package_ddecl.v");
 
-    compile(
+compile(
-        verilator_flags2 => ['--timing'],
+    verilator_flags2 => ['--timing'],
-        timing_loop => 1,
+    timing_loop => 1,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_parse_delay_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,16 +10,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_parse_delay.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_parse_delay.v");
 
-    compile(
+compile(
-        verilator_flags2 => ['--timing'],
+    verilator_flags2 => ['--timing'],
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_process.pl

@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    v_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        v_flags2 => ["--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_process_finished.pl

@@ -10,18 +10,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_process_fork.pl

@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_process_kill.pl

@@ -10,18 +10,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_process_rand.pl

@@ -10,18 +10,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    v_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        v_flags2 => ["--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_process_std.pl

@@ -12,18 +12,13 @@ scenarios(simulator => 1);
 
 top_filename("t/t_process.v");
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    v_flags2 => ["+define+T_PROCESS+std::process", "--timing"],
-}
+    );
-else {
-    compile(
-        v_flags2 => ["+define+T_PROCESS+std::process", "--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        ) if !$Self->{vlt_all};
+    ) if !$Self->{vlt_all};
-}
 
 ok(1);
 1;

test_regress/t/t_semaphore.pl

@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing -Wall"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing -Wall"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_semaphore_always.pl

@@ -10,18 +10,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_semaphore_class.pl

@@ -10,14 +10,9 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
-}
 
 ok(1);
 1;

test_regress/t/t_semaphore_std.pl

@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_semaphore.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_semaphore.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"],
+    verilator_flags2 => ["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_suspendable_deep.pl

@@ -10,14 +10,9 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--timing"],
-        );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_always.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_class.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_clkgen1.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing -Wno-MINTYPMAXDLY"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing -Wno-MINTYPMAXDLY"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_clkgen2.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_clkgen3.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_clkgen_sc.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,23 +10,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_timing_clkgen2.v");
-    skip("No coroutine support");
-}
-elsif (!$Self->have_sc) {
-    skip("No SystemC installed");
-}
-else {
-    top_filename("t/t_timing_clkgen2.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"],
+    verilator_flags2 => ["--sc --exe --timing --timescale 10ps/1ps"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_debug1.pl

@@ -10,25 +10,20 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt_all => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_timing_sched.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_timing_sched.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing"],
+    verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        all_run_flags => ["+verilator+debug"],
+    all_run_flags => ["+verilator+debug"],
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
-    if (!$Self->{vltmt}) {  # vltmt output may vary between thread exec order
+if (!$Self->{vltmt}) {  # vltmt output may vary between thread exec order
-        files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
+    files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
-    }
 }
 
 ok(1);

test_regress/t/t_timing_debug2.pl

@@ -10,25 +10,20 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt_all => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_timing_class.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_timing_class.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing"],
+    verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        all_run_flags => ["+verilator+debug"],
+    all_run_flags => ["+verilator+debug"],
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
-    if (!$Self->{vltmt}) {  # vltmt output may vary between thread exec order
+if (!$Self->{vltmt}) {  # vltmt output may vary between thread exec order
-        files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
+    files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
-    }
 }
 
 ok(1);

test_regress/t/t_timing_delay_callstack.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_dlyassign.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_events.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_fork_comb.pl

@@ -10,27 +10,22 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+# Should convert the first always into combo and detect cycle
-    skip("No coroutine support");
+compile(
-}
+    fails => 1,
-else {
+    verilator_flags2 => ["--timing"],
-    # Should convert the first always into combo and detect cycle
+    expect =>
-    compile(
+    '%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:'
-        fails => 1,
+    );
-        verilator_flags2 => ["--timing"],
-        expect =>
-            '%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:'
-        );
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"],
+    verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_fork_join.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,20 +10,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_fork_many.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_fork_nba.pl

@@ -10,14 +10,9 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --timing"],
-}
+    );
-else {
-    compile(
-        verilator_flags2 => ["--exe --timing"],
-        );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_fork_no_timing_ctrl.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2023 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_fork_taskcall.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2023 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_intra_assign.pl

@@ -10,31 +10,25 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT -fno-localize"],
+    verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT -fno-localize"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-
-}
 
 ok(1);
 1;

test_regress/t/t_timing_long.pl

@@ -56,7 +56,7 @@ gen($Self->{top_filename});
 
 if ($Self->have_coroutines) {
     compile(
-        verilator_flags2 => ["--exe --build --main --timing"],
+        verilator_flags2 => ["--exe --build --main --tim" . "ing"],
         verilator_make_cmake => 0,
         verilator_make_gmake => 0,
         make_main => 0,

test_regress/t/t_timing_nba.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_off.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_pong.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_protect.pl

@@ -10,34 +10,27 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_timing_fork_join.v");  # Contains all relevant constructs
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_timing_fork_join.v");  # Contains all relevant constructs
 
-    compile(
+compile(
-        verilator_flags2 => ["--exe --main --timing --protect-ids",
+    verilator_flags2 => ["--exe --main --timing --protect-ids",
-                             "--protect-key SECRET_KEY"],
+                         "--protect-key SECRET_KEY"],
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
-    if ($Self->{vlt_all}) {
+if ($Self->{vlt_all}) {
-        # Check for secret in any outputs
+    # Check for secret in any outputs
-        my $any;
+    my $any;
-        foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") {
+    foreach my $filename (glob $Self->{obj_dir} . "/*.[ch]*") {
-            file_grep_not($filename, qr/event[123]/i);
+        file_grep_not($filename, qr/event[123]/i);
-            file_grep_not($filename, qr/t_timing_fork_join/i);
+        file_grep_not($filename, qr/t_timing_fork_join/i);
-            $any = 1;
+        $any = 1;
     }
     $any or $Self->error("No outputs found");
-
-}
-
 }
 
 ok(1);

test_regress/t/t_timing_reentry.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_sched.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_sched_if.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_sched_nba.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_strobe.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,20 +10,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_trace.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
-    vcd_identical($Self->trace_filename, $Self->{golden_filename});
+vcd_identical($Self->trace_filename, $Self->{golden_filename});
-}
 
 ok(1);
 1;

test_regress/t/t_timing_trace_fst.pl

@@ -12,21 +12,16 @@ scenarios(simulator => 1);
 
 top_filename("t/t_timing_trace.v");
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
-    fst_identical($Self->trace_filename, $Self->{golden_filename});
+fst_identical($Self->trace_filename, $Self->{golden_filename});
-}
 
 ok(1);
 1;

test_regress/t/t_timing_wait1.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing -Wno-WAITCONST"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing -Wno-WAITCONST"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_wait2.pl

@@ -10,20 +10,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --timing --main"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_timing_wait_long.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Wilson Snyder. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,19 +10,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
+
-        verilator_flags2 => ["--exe --main --timing"],
+execute(
-        make_main => 0,
+    check_finished => 1,
-        );
+    expect_filename => $Self->{golden_filename},
+    );
 
-    execute(
-        check_finished => 1,
-        expect_filename => $Self->{golden_filename},
-        );
-}
 ok(1);
 1;

test_regress/t/t_trace_binary.pl

@@ -10,26 +10,21 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags => [# Custom as don't want -cc
-}
+                        "-Mdir $Self->{obj_dir}",
-else {
+                        "--debug-check", ],
-    compile(
+    verilator_flags2 => ['--binary --trace'],
-        verilator_flags => [# Custom as don't want -cc
+    verilator_make_cmake => 0,
-                            "-Mdir $Self->{obj_dir}",
+    verilator_make_gmake => 0,
-                            "--debug-check", ],
+    make_main => 0,
-        verilator_flags2 => ['--binary --trace'],
+    );
-        verilator_make_cmake => 0,
-        verilator_make_gmake => 0,
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
-    vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
+vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
-}
 
 ok(1);
 1;

test_regress/t/t_trace_binary_flag_off.pl

@@ -12,24 +12,19 @@ scenarios(vlt => 1);
 
 top_filename("t/t_trace_binary.v");
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags => [# Custom as don't want -cc
-}
+                        "-Mdir $Self->{obj_dir}",
-else {
+                        "--debug-check", ],
-    compile(
+    verilator_flags2 => ['--binary'],
-        verilator_flags => [# Custom as don't want -cc
+    verilator_make_cmake => 0,
-                            "-Mdir $Self->{obj_dir}",
+    verilator_make_gmake => 0,
-                            "--debug-check", ],
+    make_main => 0,
-        verilator_flags2 => ['--binary'],
+    );
-        verilator_make_cmake => 0,
-        verilator_make_gmake => 0,
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        expect_filename => $Self->{golden_filename},
+    expect_filename => $Self->{golden_filename},
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_trace_timing1.pl

@@ -10,24 +10,19 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags => [# Custom as don't want -cc
-}
+                        "-Mdir $Self->{obj_dir}",
-else {
+                        "--debug-check", ],
-    compile(
+    verilator_flags2 => ['--binary --trace'],
-        verilator_flags => [# Custom as don't want -cc
+    verilator_make_cmake => 0,
-                            "-Mdir $Self->{obj_dir}",
+    verilator_make_gmake => 0,
-                            "--debug-check", ],
+    make_main => 0,
-        verilator_flags2 => ['--binary --trace'],
+    );
-        verilator_make_cmake => 0,
-        verilator_make_gmake => 0,
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
 

test_regress/t/t_trace_ub_misaligned_address.pl

@@ -10,29 +10,24 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_trace_ub_misaligned_address.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_trace_ub_misaligned_address.v");
 
-    compile(
+compile(
-        verilator_flags2 => ["--binary --timing --trace",
+    verilator_flags2 => ["--binary --trace",
-                             "-CFLAGS -fsanitize=address,undefined",
+                         "-CFLAGS -fsanitize=address,undefined",
-                             "-LDFLAGS -fsanitize=address,undefined"],
+                         "-LDFLAGS -fsanitize=address,undefined"],
-        verilator_make_cmake => 0,
+    verilator_make_cmake => 0,
-        verilator_make_gmake => 0,
+    verilator_make_gmake => 0,
-        make_main => 0,
+    make_main => 0,
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
 
 # Make sure that there are no additional messages (such as runtime messages
 # regarding undefined behavior).
-    files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
+files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
-}
 
 ok(1);
 1;

test_regress/t/t_vlt_timing.pl

@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -12,19 +12,14 @@ scenarios(simulator => 1);
 
 top_filename("t/t_timing_off.v");
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    verilator_flags2 => ["--exe --main --timing t/t_vlt_timing.vlt"],
-}
+    make_main => 0,
-else {
+    );
-    compile(
-        verilator_flags2 => ["--exe --main --timing t/t_vlt_timing.vlt"],
-        make_main => 0,
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_wait_timing.pl

@@ -10,21 +10,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(vlt => 1);
 
-if (!$Self->have_coroutines) {
+top_filename("t/t_wait.v");
-    skip("No coroutine support");
-}
-else {
-    top_filename("t/t_wait.v");
 
-    compile(
+compile(
-        timing_loop => 1,
+    timing_loop => 1,
-        verilator_flags2 => ["--timing -Wno-WAITCONST"],
+    verilator_flags2 => ["--timing -Wno-WAITCONST"],
-        );
+    );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;

test_regress/t/t_while_timing_control.pl

@@ -12,19 +12,14 @@ scenarios(simulator => 1);
 
 $Self->{main_time_multiplier} = 10e-7 / 10e-9;
 
-if (!$Self->have_coroutines) {
+compile(
-    skip("No coroutine support");
+    timing_loop => 1,
-}
+    verilator_flags2 => ['--timing -Wno-ZERODLY'],
-else {
+    );
-    compile(
-        timing_loop => 1,
-        verilator_flags2 => ['--timing -Wno-ZERODLY'],
-        );
 
-    execute(
+execute(
-        check_finished => 1,
+    check_finished => 1,
-        );
+    );
-}
 
 ok(1);
 1;