Fix loss of events due to bit shift (#7670)
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@ -920,7 +920,7 @@ class AwaitBeforeTrigVisitor final : public VNVisitor {
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const size_t idx = m_trigKit.senItem2TrigIdx(senItemp);
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if (usedTriggers.find(idx) != usedTriggers.end()) {
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usedTrigsToUsingTrees[idx / TriggerKit::WORD_SIZE]
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[1 << (idx % TriggerKit::WORD_SIZE)]
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[size_t{1} << (idx % TriggerKit::WORD_SIZE)]
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.push_back(shedp);
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}
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}
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--timing'])
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test.execute()
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test.passes()
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@ -0,0 +1,40 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t(
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input clk
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);
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int cyc = 0;
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int cnt = 0;
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event ev[128];
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always @(posedge clk) begin
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++cyc;
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if (cyc >= 3) begin
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`checkd(cnt, 128);
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$finish;
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end
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end
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for (genvar i = 0; i < 128; ++i) begin : gen_ev_wait
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always @(posedge clk) begin
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if (cyc < 3) begin
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fork
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begin
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->ev[i];
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@(ev[i]);
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cnt++;
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end
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join_none
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end
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end
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end
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endmodule
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