Fix over-shift structure optimization error, bug803.

Changes

@@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix dpiGetContext in dotted scopes, bug740. [Geoff Barrett]
 
+****  Fix over-shift structure optimization error, bug803. [Jeff Bush]
+
 
 * Verilator 3.862 2014-06-10
 

src/V3Expand.cpp

@@ -583,11 +583,15 @@ private:
 								     newSelBitBit(lhsp->lsbp()),
 								     VL_WORDSIZE)),
 					  oldvalp);
+
+		// Restrict the shift amount to 0-31, see bug804.
+		AstNode* shiftp = new AstAnd(nodep->fileline(), lhsp->lsbp()->cloneTree(true),
+					     new AstConst(nodep->fileline(), VL_WORDSIZE-1));
 		AstNode* newp = new AstOr (lhsp->fileline(),
 					   oldvalp,
 					   new AstShiftL (lhsp->fileline(),
 							  rhsp,
-							  lhsp->lsbp()->cloneTree(true),
+							  shiftp,
 							  VL_WORDSIZE));
 		newp = new AstAssign (nodep->fileline(),
 				      new AstWordSel (nodep->fileline(),

test_regress/t/t_struct_unaligned.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+# Note: need to run at a higher optimization level to reproduce the issue
+$Self->{benchmark} = 1;
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_struct_unaligned.v

@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator:
+//  Test an error where a shift amount was out of bounds and the compiler treats the
+//  value as undefined (Issue #803)
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Jeff Bush.
+
+module t (/*AUTOARG*/
+    // Inputs
+    clk
+    );
+    input clk;
+
+    struct packed {
+	logic flag;
+	logic [130:0] data;
+    } foo[1];
+
+    integer cyc=0;
+
+    // Test loop
+    always @ (posedge clk) begin
+	cyc <= cyc + 1;
+	foo[0].data <= 0;
+	foo[0].flag <= !foo[0].flag;
+	if (cyc==10) begin
+	   if (foo[0].data != 0) begin
+	   	$display("bad data value %x", foo[0].data);
+		$stop;
+	   end
+	   $write("*-* All Finished *-*\n");
+	   $finish;
+	end
+    end
+endmodule