luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix ==? and !=? with X values.

This commit is contained in:
Wilson Snyder 2024-07-28 14:40:55 -04:00
parent 8707c88787
commit 3a659d460d
2 changed files with 34 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/V3Number.cpp
View File

@ -1696,12 +1696,14 @@ V3Number& V3Number::opWildEq(const V3Number& lhs, const V3Number& rhs) {
NUM_ASSERT_LOGIC_ARGS2(lhs, rhs); NUM_ASSERT_LOGIC_ARGS2(lhs, rhs);
char outc = 1; char outc = 1;
for (int bit = 0; bit < std::max(lhs.width(), rhs.width()); bit++) { for (int bit = 0; bit < std::max(lhs.width(), rhs.width()); bit++) {
if (!rhs.bitIsXZ(bit) && lhs.bitIs(bit) != rhs.bitIs(bit)) { if (!rhs.bitIsXZ(bit)) {
if (lhs.bitIs(bit) != rhs.bitIs(bit)) {
outc = 0; outc = 0;
goto last; goto last;
} }
if (lhs.bitIsXZ(bit)) outc = 'x'; if (lhs.bitIsXZ(bit)) outc = 'x';
} }
}
last: last:
return setSingleBits(outc); return setSingleBits(outc);
} }
@ -1711,12 +1713,14 @@ V3Number& V3Number::opWildNeq(const V3Number& lhs, const V3Number& rhs) {
NUM_ASSERT_LOGIC_ARGS2(lhs, rhs); NUM_ASSERT_LOGIC_ARGS2(lhs, rhs);
char outc = 0; char outc = 0;
for (int bit = 0; bit < std::max(lhs.width(), rhs.width()); bit++) { for (int bit = 0; bit < std::max(lhs.width(), rhs.width()); bit++) {
if (!rhs.bitIsXZ(bit) && lhs.bitIs(bit) != rhs.bitIs(bit)) { if (!rhs.bitIsXZ(bit)) {
if (lhs.bitIs(bit) != rhs.bitIs(bit)) {
outc = 1; outc = 1;
goto last; goto last;
} }
if (lhs.bitIsXZ(bit)) outc = 'x'; if (lhs.bitIsXZ(bit)) outc = 'x';
} }
}
last: last:
return setSingleBits(outc); return setSingleBits(outc);
} }

22
test_regress/t/t_math_eq.v
View File

@ -4,6 +4,9 @@
// any use, without warranty, 2007 by Wilson Snyder. // any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t (/*AUTOARG*/ module t (/*AUTOARG*/
// Inputs // Inputs
clk clk
@ -35,6 +38,25 @@ module t (/*AUTOARG*/
// What checksum will we end up with // What checksum will we end up with
`define EXPECTED_SUM 64'h1a0d07009b6a30d2 `define EXPECTED_SUM 64'h1a0d07009b6a30d2
initial begin
`checkh(3'b101 ==? 3'b100, 1'b0);
`checkh(3'b101 ==? 3'b101, 1'b1);
`checkh(3'b100 ==? 3'b10x, 1'b1);
`checkh(3'b101 ==? 3'b10x, 1'b1);
`checkh(3'b10x ==? 3'b10?, 1'b1);
`checkh(3'b110 ==? 3'b10?, 1'b0);
`checkh(3'b111 ==? 3'b10?, 1'b0);
`checkh(3'b11x ==? 3'b10?, 1'b0);
`checkh(3'b101 !=? 3'b100, !1'b0);
`checkh(3'b101 !=? 3'b101, !1'b1);
`checkh(3'b100 !=? 3'b10x, !1'b1);
`checkh(3'b101 !=? 3'b10x, !1'b1);
`checkh(3'b10x !=? 3'b10?, !1'b1);
`checkh(3'b110 !=? 3'b10?, !1'b0);
`checkh(3'b111 !=? 3'b10?, !1'b0);
`checkh(3'b11x !=? 3'b10?, !1'b0);
end
// Test loop // Test loop
always @ (posedge clk) begin always @ (posedge clk) begin
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE