Fixes #7290. Fixes #7685.
This commit is contained in:
Yilou Wang
GitHub
parent
e965fb92de
commit
39b9901032
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@ -818,6 +818,91 @@ class SvaNfaBuilder final {
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return result;
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}
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// until / until_with (weak forms only) per IEEE 1800-2023 16.12.12.
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// Topology: combinational wait vertex with self-feeding state register.
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// entry --link[T]--> waitC
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// waitR --link[T]--> waitC (back-loop)
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// waitC --edge[##1, sampled(p) && !sampled(q)]--> waitR (continue)
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// waitC --link[REQUIRE, rejectOnFail]--> sink (per-cycle fail)
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// waitC --link[T]--> match (added by wireMatchAndMidSources;
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// accept condition rides via finalCondp)
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// waitC is m_isUnbounded so the terminal-match link contributes only to
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// terminalActive, not to rejectBase (which would otherwise spuriously fire
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// every cycle q is false). Per-cycle reject comes from the explicit
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// rejectOnFail link to the sink vertex.
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//
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// Weak non-overlapping (p until q):
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// REQUIRE = sampled(p) || sampled(q) accept = sampled(q)
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// Weak overlapping (p until_with q):
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// REQUIRE = sampled(p) accept = sampled(p) && sampled(q)
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BuildResult buildUntil(AstUntil* nodep, SvaStateVertex* entryVtxp, bool isTopLevelStep) {
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FileLine* const flp = nodep->fileline();
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if (!isTopLevelStep) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: 'until' in complex property expression");
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return BuildResult::failWithError();
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}
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if (nodep->isStrong()) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: s_until"
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<< (nodep->isOverlapping() ? "_with" : "")
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<< " (in property expresion)");
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return BuildResult::failWithError();
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}
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AstNodeExpr* const lhsp = nodep->lhsp();
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AstNodeExpr* const rhsp = nodep->rhsp();
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const auto hasSeq = [](const AstNodeExpr* ep) {
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return ep->exists([](const AstNodeExpr* np) { return np->isMultiCycleSva(); });
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};
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if (hasSeq(lhsp) || hasSeq(rhsp)) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: 'until' in complex property expression");
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return BuildResult::failWithError();
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}
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const bool ov = nodep->isOverlapping();
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AstNodeExpr* const lhsBitp = nodep->lhsp();
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AstNodeExpr* const rhsBitp = nodep->rhsp();
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// p hoist count: continue, require (ov: 1 use; nov: 1 use). At least 2 uses.
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AstVar* const pHoistp = tryHoistSampled(lhsBitp, flp, 2);
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// q hoist count: continue (1) + require nov (1) = 2; ov: continue only (1).
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AstVar* const qHoistp = ov ? nullptr : tryHoistSampled(rhsBitp, flp, 2);
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SvaStateVertex* const waitCp = scopedCreateVertex();
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SvaStateVertex* const waitRp = scopedCreateVertex();
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waitCp->m_isUnbounded = true;
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// Entry and back-loop Links carry no condition; throughout-folding still applies.
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guardedLink(entryVtxp, waitCp, flp);
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guardedLink(waitRp, waitCp, flp);
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// Continue clocked edge: p && !q advances to next-cycle wait.
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AstNodeExpr* const contCondp
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= new AstLogAnd{flp, sampledRefOrClone(pHoistp, lhsBitp, flp),
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new AstLogNot{flp, sampledRefOrClone(qHoistp, rhsBitp, flp)}};
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guardedEdge(waitCp, waitRp, contCondp, flp);
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// Reject sink: fires when require-condition is false.
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SvaStateVertex* const sinkVtxp = m_graph.createStateVertex();
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sinkVtxp->m_isRejectSink = true;
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AstNodeExpr* requireCondp;
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if (ov) {
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requireCondp = sampledRefOrClone(pHoistp, lhsBitp, flp);
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} else {
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requireCondp = new AstLogOr{flp, sampledRefOrClone(pHoistp, lhsBitp, flp),
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sampledRefOrClone(qHoistp, rhsBitp, flp)};
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}
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SvaTransEdge* const rejEdgep = m_graph.addLink(waitCp, sinkVtxp, requireCondp);
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rejEdgep->m_rejectOnFail = true;
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// Accept condition rides via finalCondp; assembleResult $sampled-wraps it.
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AstNodeExpr* acceptCondp;
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if (ov) {
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acceptCondp
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= new AstLogAnd{flp, lhsBitp->cloneTreePure(false), rhsBitp->cloneTreePure(false)};
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} else {
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acceptCondp = rhsBitp->cloneTreePure(false);
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}
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return {waitCp, acceptCondp, {}};
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}
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// IEEE 1800-2023 16.12.14 property abort operators. Sync and async share
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// the same NFA encoding: AstSampled already gives matured values at every
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// maturing clocking event, and async firing "between clocks" is not
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@ -948,6 +1033,9 @@ public:
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implp->isOverlapped(), implp->isFollowedBy(),
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implp->lhsp(), implp->fileline());
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}
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if (AstUntil* const untilp = VN_CAST(nodep, Until)) {
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return buildUntil(untilp, entryVtxp, isTopLevelStep);
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}
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// Boolean leaf (including LogAnd): return as finalCond
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return {entryVtxp, nodep, {}};
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}
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@ -1836,6 +1924,25 @@ class AssertNfaVisitor final : public VNVisitor {
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});
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}
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// Bare `assert property (p until q)` with boolean operands stays on
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// V3AssertPre's AstLoop lowering, which preserves per-attempt action-block
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// firings that this NFA's single-bit aggregated state cannot. NFA still
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// owns strong forms, sequence operands, and any embedding inside a
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// multi-cycle context (implication consequent, or/and operands, etc.).
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static bool isBareTopLevelUntil(AstNode* propp) {
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AstNode* p = propp;
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if (AstPropSpec* const specp = VN_CAST(p, PropSpec)) p = specp->propp();
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while (AstLogNot* const notp = VN_CAST(p, LogNot)) p = notp->lhsp();
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AstUntil* const untilp = VN_CAST(p, Until);
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if (!untilp) return false;
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if (untilp->isStrong()) return false;
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const auto hasSeq = [](const AstNodeExpr* ep) {
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return ep->exists([](const AstNodeExpr* np) { return np->isMultiCycleSva(); });
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};
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if (hasSeq(untilp->lhsp()) || hasSeq(untilp->rhsp())) return false;
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return true;
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}
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struct PropertyParts final {
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AstNodeExpr* triggerExprp = nullptr;
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AstNodeExpr* seqExprp = nullptr;
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@ -2083,6 +2190,7 @@ class AssertNfaVisitor final : public VNVisitor {
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AstNode* const propp = assertp->propp();
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if (!hasMultiCycleExpr(propp)) return;
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if (isBareTopLevelUntil(propp)) return;
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PropertyParts parts = decomposeProperty(propp);
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UASSERT_OBJ(parts.seqExprp, propp, "Property body must be an expression");
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@ -2908,6 +2908,7 @@ public:
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bool cleanOut() const override { V3ERROR_NA_RETURN(""); }
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int instrCount() const override { return widthInstrs(); }
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bool sameNode(const AstNode* /*samep*/) const override { return true; }
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bool isMultiCycleSva() const override { return true; }
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bool isStrong() const { return m_strong; }
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bool isOverlapping() const { return m_overlapping; }
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};
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@ -1715,6 +1715,12 @@ class WidthVisitor final : public VNVisitor {
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if (m_vup->prelim()) {
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iterateCheckBool(nodep, "LHS", nodep->lhsp(), BOTH);
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iterateCheckBool(nodep, "RHS", nodep->rhsp(), BOTH);
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// Coerce unsized constant operands (e.g. literal 0/1) to actual
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// 1-bit width; iterateCheckBool keeps widthMin-fitting unsized
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// constants at their nominal 32-bit width, which trips the
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// downstream NFA lowering's Log* chains in V3AssertNfa.
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if (nodep->lhsp()->width() != 1) fixWidthReduce(nodep->lhsp());
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if (nodep->rhsp()->width() != 1) fixWidthReduce(nodep->rhsp());
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nodep->dtypeSetBit();
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}
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}
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@ -1,22 +1,26 @@
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%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:70:14: Logical operator IMPLICATION expects 1 bit on the RHS, but RHS's CMETHODHARD 'at' generates 8 bits.
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%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:72:14: Logical operator IMPLICATION expects 1 bit on the RHS, but RHS's CMETHODHARD 'at' generates 8 bits.
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: ... note: In instance 't.ieee'
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70 | $rose(a) |-> q[0];
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72 | $rose(a) |-> q[0];
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| ^~~
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... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
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... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
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%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:75:29: Logical operator SEXPR expects 1 bit on the exprp, but exprp's CMETHODHARD 'at' generates 8 bits.
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%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:77:29: Logical operator SEXPR expects 1 bit on the exprp, but exprp's CMETHODHARD 'at' generates 8 bits.
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: ... note: In instance 't.ieee'
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75 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
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77 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
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| ^~
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%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:96:31: Logical operator SEXPR expects 1 bit on the exprp, but exprp's VARREF 'b' generates 32 bits.
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%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:98:31: Logical operator SEXPR expects 1 bit on the exprp, but exprp's VARREF 'b' generates 32 bits.
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: ... note: In instance 't.ieee'
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96 | assert property (@clk not a ##1 b);
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98 | assert property (@clk not a ##1 b);
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:49: Unsupported: 'until' in complex property expression
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:39: Unsupported: 'until' in complex property expression
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: ... note: In instance 't'
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47 | assert property (@(posedge clk) val until val until val) $display("[%0t] nested until, fileline:%d", $time, 47);
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| ^~~~~
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| ^~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: 'until' in complex property expression
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: ... note: In instance 't'
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49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
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| ^~~~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:51:39: Unsupported: s_until (in property expresion)
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: ... note: In instance 't'
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51 | assert property (@(posedge clk) val s_until !val) $display("[%0t] s_until, fileline:%d", $time, 51);
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@ -25,16 +29,8 @@
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: ... note: In instance 't'
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53 | assert property (@(posedge clk) val s_until_with val) $display("[%0t] s_until_with, fileline:%d", $time, 53);
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| ^~~~~~~~~~~~
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%Error: t/t_property_sexpr_unsup.v:49:50: Duplicate declaration of block: '__VcycleDly_h########__2__block'
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: ... note: In instance 't'
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49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
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| ^~
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t/t_property_sexpr_unsup.v:49:50: ... Location of original declaration
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49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
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| ^~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Internal Error: t/t_property_sexpr_unsup.v:45:44: ../V3Ast.cpp:#: AstPExpr::bodyp() cannot have a non-nullptr nextp()
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: ... note: In instance 't'
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45 | assert property (@(posedge clk) ##1 (val until val)) $display("[%0t] until in sequence, fileline:%d", $time, 45);
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| ^~~~~
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... This fatal error may be caused by the earlier error(s); resolve those first.
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:55:40: Unsupported: 'until' in complex property expression
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: ... note: In instance 't'
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55 | assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, 55);
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| ^~~~~
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%Error: Exiting due to
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@ -1,8 +1,12 @@
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:49: Unsupported: 'until' in complex property expression
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:39: Unsupported: 'until' in complex property expression
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: ... note: In instance 't'
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47 | assert property (@(posedge clk) val until val until val) $display("[%0t] nested until, fileline:%d", $time, 47);
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| ^~~~~
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| ^~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: 'until' in complex property expression
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: ... note: In instance 't'
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49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
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| ^~~~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:51:39: Unsupported: s_until (in property expresion)
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: ... note: In instance 't'
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51 | assert property (@(posedge clk) val s_until !val) $display("[%0t] s_until, fileline:%d", $time, 51);
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@ -11,16 +15,8 @@
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: ... note: In instance 't'
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53 | assert property (@(posedge clk) val s_until_with val) $display("[%0t] s_until_with, fileline:%d", $time, 53);
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| ^~~~~~~~~~~~
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%Error: t/t_property_sexpr_unsup.v:49:50: Duplicate declaration of block: '__VcycleDly_h########__2__block'
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: ... note: In instance 't'
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49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
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| ^~
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t/t_property_sexpr_unsup.v:49:50: ... Location of original declaration
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49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
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| ^~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Internal Error: t/t_property_sexpr_unsup.v:45:44: ../V3Ast.cpp:#: AstPExpr::bodyp() cannot have a non-nullptr nextp()
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: ... note: In instance 't'
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45 | assert property (@(posedge clk) ##1 (val until val)) $display("[%0t] until in sequence, fileline:%d", $time, 45);
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| ^~~~~
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... This fatal error may be caused by the earlier error(s); resolve those first.
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:55:40: Unsupported: 'until' in complex property expression
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: ... note: In instance 't'
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55 | assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, 55);
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| ^~~~~
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%Error: Exiting due to
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@ -52,6 +52,8 @@ module t ( /*AUTOARG*/
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assert property (@(posedge clk) val s_until_with val) $display("[%0t] s_until_with, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, `__LINE__);
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property prop_implication;
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##1 cyc == 4 |-> 1;
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endproperty
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--assert'])
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test.execute()
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test.passes()
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@ -0,0 +1,64 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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reg [63:0] crc;
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// CRC bits chosen far apart to keep antecedent/consequent uncorrelated.
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wire trig = crc[0];
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wire c = crc[10];
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wire d = crc[20] | crc[40];
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int fail_nonoverlap = 0;
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int fail_overlap = 0;
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// Weak non-overlapping until as implication consequent.
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// IEEE 1800-2023 16.12.12: c true at every tick until at least one tick
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// before d holds. Cycle-aggregated reject fires when c=0 and d=0 in a cycle
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// where the consequent attempt is still live.
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assert property (@(posedge clk) trig |=> c until d)
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else fail_nonoverlap = fail_nonoverlap + 1;
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// Weak overlapping (until_with) as implication consequent.
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assert property (@(posedge clk) trig |=> c until_with d)
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else fail_overlap = fail_overlap + 1;
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// Exercises buildUntil's bit-coerce branch: V3Width leaves unsized constants
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// at their nominal 32-bit dtype, so hoist-temp assignments need an explicit
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// 1-bit reduction. The assertion itself is trivially true (q == 1).
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assert property (@(posedge clk) trig |=> 0 until 1);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x trig=%b c=%b d=%b\n", $time, cyc, crc, trig, c, d);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc == 99) begin
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// Counts reflect NFA per-cycle reject aggregation, not Questa's
|
||||
// per-attempt action_block firing; the two differ by a small constant
|
||||
// (see PR description for the model gap). Test is a regression for
|
||||
// "no internal error on `until` as |=> consequent" (issue #7548).
|
||||
`checkd(fail_nonoverlap, 7);
|
||||
`checkd(fail_overlap, 22);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue