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Tests: Remove CRs.

This commit is contained in:
Wilson Snyder 2019-06-04 20:37:16 -04:00
parent 4e115d4b69
commit 38ad8727af
3 changed files with 47 additions and 47 deletions
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38
test_regress/t/t_sv_cpu_code/pad_gnd.sv
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@ -1,19 +1,19 @@
// DESCRIPTION: Verilator: Large test for SystemVerilog // DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use, // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012. // without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation. // Contributed by M W Lund, Atmel Corporation.
//***************************************************************************** //*****************************************************************************
// PAD_GND - Ground Supply Pad (Dummy!!!!) // PAD_GND - Ground Supply Pad (Dummy!!!!)
//***************************************************************************** //*****************************************************************************
module pad_gnd module pad_gnd
#( parameter ID = 0 ) #( parameter ID = 0 )
( (
inout wire pad inout wire pad
); );
assign pad = 1'b0; assign pad = 1'b0;
endmodule // pad_gnd endmodule // pad_gnd

38
test_regress/t/t_sv_cpu_code/pad_vdd.sv
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@ -1,19 +1,19 @@
// DESCRIPTION: Verilator: Large test for SystemVerilog // DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use, // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012. // without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation. // Contributed by M W Lund, Atmel Corporation.
//***************************************************************************** //*****************************************************************************
// PAD_VDD - VDD Supply Pad (Dummy!!!!) // PAD_VDD - VDD Supply Pad (Dummy!!!!)
//***************************************************************************** //*****************************************************************************
module pad_vdd module pad_vdd
#( parameter ID = 0 ) #( parameter ID = 0 )
( (
inout wire pad inout wire pad
); );
assign pad = 1'b1; assign pad = 1'b1;
endmodule // pad_vdd endmodule // pad_vdd

18
test_regress/t/t_sv_cpu_code/timescale.sv
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@ -1,9 +1,9 @@
// DESCRIPTION: Verilator: Large test for SystemVerilog // DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use, // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012. // without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation. // Contributed by M W Lund, Atmel Corporation.
// **** Set simulation time scale **** // **** Set simulation time scale ****
`timescale 1ns/1ps `timescale 1ns/1ps