Fix false unused warning on interfaces, bug1241.

Changes

@@ -12,6 +12,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add error when driving input-only modport.
 
+****  Fix false unused warning on interfaces, bug1241. [Laurens van Dam]
+
 
 * Verilator 3.914 2017-10-14
 

src/V3Undriven.cpp

@@ -175,7 +175,11 @@ public:
 	    if (allU) m_usedWhole = true;
 	    if (allD) m_drivenWhole = true;
 	    // Test results
-	    if (allU && allD) {
+	    if (nodep->isIfaceRef()) {
+		// For interface top level we don't do any tracking
+		// Ideally we'd report unused instance cells, but presumably a signal inside one
+		// would get reported as unused
+	    } else if (allU && allD) {
 		// It's fine
 	    } else if (!anyD && !anyU) {
 		// UNDRIVEN is considered more serious - as is more likely a bug,
@@ -258,7 +262,7 @@ private:
 	}
     }
 
-    void warnAlwCombOrder(AstVarRef* nodep) {
+    void warnAlwCombOrder(AstNodeVarRef* nodep) {
 	AstVar* varp = nodep->varp();
 	if (!varp->isParam() && !varp->isGenVar() && !varp->isUsedLoopIdx()
 	    && !m_inBBox   // We may have falsely considered a SysIgnore as a driver
@@ -292,7 +296,7 @@ private:
 	nodep->iterateChildren(*this);
     }
     virtual void visit(AstSel* nodep) {
-	AstVarRef* varrefp = nodep->fromp()->castVarRef();
+	AstNodeVarRef* varrefp = nodep->fromp()->castNodeVarRef();
 	AstConst* constp = nodep->lsbp()->castConst();
 	if (varrefp && constp && !constp->num().isFourState()) {
 	    for (int usr=1; usr<(m_alwaysp?3:2); ++usr) {
@@ -313,7 +317,7 @@ private:
 	    nodep->iterateChildren(*this);
 	}
     }
-    virtual void visit(AstVarRef* nodep) {
+    virtual void visit(AstNodeVarRef* nodep) {
 	// Any variable
 	for (int usr=1; usr<(m_alwaysp?3:2); ++usr) {
 	    UndrivenVarEntry* entryp = getEntryp (nodep->varp(), usr);

test_regress/t/t_lint_unused_iface.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"],
+    fails=>0,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;
+

test_regress/t/t_lint_unused_iface.v

@@ -0,0 +1,59 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+interface dummy_if ();
+   logic signal;
+
+   modport slave
+     (
+      input signal
+      );
+
+   modport master
+     (
+      output signal
+      );
+endinterface: dummy_if
+
+module sub
+  (
+   input wire  signal_i,
+   output wire signal_o,
+
+   dummy_if.master dummy_in,
+   dummy_if.slave dummy_out
+   );
+
+   assign dummy_in.signal = signal_i;
+   assign signal_o = dummy_out.signal;
+endmodule
+
+
+module t (/*AUTOARG*/
+   // Outputs
+   signal_o,
+   // Inputs
+   signal_i
+   );
+   input signal_i;
+   output signal_o;
+
+   // verila tor lint_off UUSD
+   // verila tor lint_off UNDRIVEN
+   dummy_if dummy_if ();
+   // verila tor lint_on UUSD
+   // verila tor lint_on UNDRIVEN
+
+   dummy_if uusd_if ();
+
+   sub sub
+     (
+      .signal_i(signal_i),
+      .signal_o(signal_o),
+      .dummy_in(dummy_if),
+      .dummy_out(dummy_if)
+      );
+
+endmodule

test_regress/t/t_lint_unused_iface_bad.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect =>
+'%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:\d+: Signal is not driven: sig_udrv
+%Warning-UNDRIVEN: Use .*
+%Warning-UNUSED: t/t_lint_unused_iface_bad.v:\d+: Signal is not used: sig_uusd
+%Error: Exiting due to .*',
+    );
+
+ok(1);
+1;
+

test_regress/t/t_lint_unused_iface_bad.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+interface dummy_if ();
+   logic sig_udrv;
+   logic sig_uusd;
+endinterface: dummy_if
+
+module sub
+  (
+   dummy_if dummy
+   );
+
+   assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv;
+endmodule
+
+
+module t (/*AUTOARG*/);
+
+   dummy_if dummy ();
+
+   sub sub
+     (.dummy(dummy)
+      );
+
+endmodule