Ignore SystemVerilog timeunit and timeprecision

Changes

@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 ***  Suppress width warnings between constant strings and wider vectors.
      [Rodney Sinclair]
 
+**** Ignore SystemVerilog timeunit and timeprecision.
+
 **** Expand environment variables in -f input files.  [Lawrence Butcher]
 
 **** Report error if port declaration is missing; bug32. [Guy-Armand Kamendje]

bin/verilator

@@ -1559,6 +1559,10 @@ full nor unique.
 
 All specify blocks and timing checks are ignored.
 
+=item timeunit, timeprecision
+
+All timing control statements are ignored.
+
 =item uwire
 
 Verilator does not perform warning checking on uwires, it treats the uwire

src/verilog.l

@@ -357,6 +357,8 @@ escid	\\[^ \t\f\r\n]+
   "iff"			{yylval.fileline = CRELINE(); return yIFF;}
   "priority"		{yylval.fileline = CRELINE(); return yPRIORITY;}
   "static"		{yylval.fileline = CRELINE(); return ySTATIC;}
+  "timeprecision"	{yylval.fileline = CRELINE(); return yTIMEPRECISION;}
+  "timeunit"		{yylval.fileline = CRELINE(); return yTIMEUNIT;}
   "unique"		{yylval.fileline = CRELINE(); return yUNIQUE;}
   /*     Generic unsupported warnings */
   /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
@@ -426,8 +428,6 @@ escid	\\[^ \t\f\r\n]+
   "tagged"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "this"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "throughout"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
-  "timeprecision"	{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
-  "timeunit"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "type"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "typedef"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "var"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
@@ -694,7 +694,7 @@ escid	\\[^ \t\f\r\n]+
 			}
   [0-9][_0-9]*(\.[_0-9]+)?(fs|ps|ns|us|ms|s|step) {
 			  yylval.cdouble = 0;  /* Only for times, not used yet */
-                          return yaFLOATNUM;
+                          return yaTIMENUM;
 			}
 }
 

src/verilog.y

@@ -141,6 +141,8 @@ class AstSenTree;
 
 // IEEE: integral_number
 %token<nump>		yaINTNUM	"INTEGER NUMBER"
+// IEEE: time_literal + time_unit
+%token<cdouble>		yaTIMENUM	"TIME NUMBER"
 // IEEE: string_literal
 %token<strp>		yaSTRING	"STRING"
 %token<fileline>	yaTIMINGSPEC	"TIMING SPEC ELEMENT"
@@ -213,6 +215,8 @@ class AstSenTree;
 %token<fileline>	ySUPPLY0	"supply0"
 %token<fileline>	ySUPPLY1	"supply1"
 %token<fileline>	yTASK		"task"
+%token<fileline>	yTIMEPRECISION	"timeprecision"
+%token<fileline>	yTIMEUNIT	"timeunit"
 %token<fileline>	yTRI		"tri"
 %token<fileline>	yTRUE		"true"
 %token<fileline>	yUNIQUE		"unique"
@@ -429,7 +433,7 @@ statePop:	/* empty */			 	{ V3Read::statePop(); }
 // Files
 
 fileE:		/* empty */				{ }
-	|	file					{ }
+	|       timeunitsDeclE 	file		      	{ }
 	;
 
 file:		description				{ }
@@ -440,13 +444,26 @@ file:		description				{ }
 description:	moduleDecl				{ }
 	;
 
+// IEEE: timeunits_declaration + empty
+timeunitsDeclE: /*empty*/                                                       { }
+        |	yTIMEUNIT  yaTIMENUM ';'					{ }
+	| 	yTIMEPRECISION  yaTIMENUM ';'					{ }
+	| 	yTIMEUNIT  yaTIMENUM ';'  yTIMEPRECISION  yaTIMENUM  ';' 	{ }
+	| 	yTIMEPRECISION yaTIMENUM ';' yTIMEUNIT yaTIMENUM ';'		{ }
+	;
+
 //**********************************************************************
 // Module headers
 
 // IEEE: module_declaration:
-moduleDecl:	modHdr modParE modPortsE ';' modItemListE yENDMODULE endLabelE
+moduleDecl:	modHeader  timeunitsDeclE modItemListE yENDMODULE endLabelE
+			{ if ($3) $1->addStmtp($3); }
+	;
+
+modHeader<modulep>:
+		modHdr modParE modPortsE ';'
 			{ $1->modTrace(V3Parse::s_trace);  // Stash for implicit wires, etc
-			  if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($5) $1->addStmtp($5); }
+			  if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); }
 	;
 
 modHdr<modulep>:
@@ -723,6 +740,7 @@ dlyTerm<nodep>:
 		yaID 					{ $$ = NULL; }
 	|	yaINTNUM 				{ $$ = NULL; }
 	|	yaFLOATNUM 				{ $$ = NULL; }
+	|	yaTIMENUM 				{ $$ = NULL; }
 	;
 
 // IEEE: mintypmax_expression and constant_mintypmax_expression

test_regress/t/t_inst_sv.v

@@ -8,6 +8,11 @@ module t (/*AUTOARG*/
    clk
    );
 
+`ifdef verilator   // Otherwise need it in every module, including test, but that'll make a mess
+   timeunit 1ns;
+   timeprecision 1ns;
+`endif
+
    input clk;
    integer cyc; initial cyc=1;