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Commentary: Changes update

This commit is contained in:
Wilson Snyder 2026-07-19 13:31:48 -04:00
parent 185a49e628
commit 3813249826
7 changed files with 102 additions and 55 deletions
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11
Changes
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@ -20,9 +20,12 @@ Verilator 5.051 devel
* Add user-provided DPI-C function declarations (#7626) (#7893). [Jakub Michalski]
* Add error on static virtual functions (#7932). [Igor Zaworski, Antmicro Ltd.]
* Support a sequence used as an event control (#7797) (#7846). [Yilou Wang]
* Support `[\*N:$]` consecutive repetition (#7940). [Artur Bieniek, Antmicro Ltd.]
* Support dynamic containers in unique constraints (#7947). [Adam Kostrzewski, Antmicro Ltd.]
* Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
* Optimize more always blocks in DFG (#7775). [Geza Lore, Testorrent USA, Inc.]
* Optimize assertion NFAs using bit-vector ring buffers (#7885). [Artur Bieniek, Antmicro Ltd.]
* Optimize VPI symbol registration and scope construction (#7936). [Nick Brereton]
* Fix $display accepting streaming concat arguments (#7663) (#7890). [Jaeuk Lee]
* Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
* Fix unique0 case side effects (#7787). [Pawel Klopotek]
@ -42,7 +45,15 @@ Verilator 5.051 devel
* Fix release of forced port nets (#7907) (#7901). [Artur Bieniek, Antmicro Ltd.]
* Fix VL_TO_STRING function for array of structs (#7912). [Kornel Uriasz, Antmicro Ltd.]
* Fix queues falling into wrong template spec (#7914). [Adam Kostrzewski, Antmicro Ltd.]
* Fix type resolution when a local name shadows a type name (#7915). [Pawel Klopotek]
* Fix crash streaming an unpacked array of unpacked structs (#7917). [Nick Brereton]
* Fix streaming concat as output-port lvalue into unpacked struct (#7918). [Nick Brereton]
* Fix dropping variable writes across opaque calls (#7921) (#7933). [Philip Axer]
* Fix dynamic array handling in solve...before (#7922). [Kornel Uriasz, Antmicro Ltd.]
* Fix unlinked error with function call in derived class parameter (#7923). [Mateusz Gancarz, Antmicro Ltd.]
* Fix class parameter resolution (#7935).
* Fix FSM detection of coverage-only branches (#7941) (#7942). [Patrick Creighton]
* Fix sampled-value clocks in repeated assertions (#7944). [Artur Bieniek, Antmicro Ltd.]
Verilator 5.050 2026-07-01

16
test_regress/t/t_constraint_unq_arr.v
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@ -45,8 +45,7 @@ module t;
for (int i = 0; i < darr.size(); i++) begin
for (int j = i + 1; j < darr.size(); j++) begin
if (darr[i] == darr[j]) begin
$error("UNIQUENESS VIOLATION: darr[%0d] == darr[%0d] == 0x%h", i, j,
darr[i]);
$error("UNIQUENESS VIOLATION: darr[%0d] == darr[%0d] == 0x%h", i, j, darr[i]);
return 0;
end
end
@ -55,8 +54,7 @@ module t;
for (int i = 0; i < queue.size(); i++) begin
for (int j = i + 1; j < queue.size(); j++) begin
if (queue[i] == queue[j]) begin
$error("UNIQUENESS VIOLATION: queue[%0d] == queue[%0d] == 0x%h", i, j,
queue[i]);
$error("UNIQUENESS VIOLATION: queue[%0d] == queue[%0d] == 0x%h", i, j, queue[i]);
return 0;
end
end
@ -65,8 +63,7 @@ module t;
for (int i = 0; i < queue_c.size(); i++) begin
for (int j = i + 1; j < queue_c.size(); j++) begin
if (queue_c[i] == queue_c[j]) begin
$error("UNIQUENESS VIOLATION: queue_c[%0d] == queue_c[%0d] == 0x%h", i, j,
queue_c[i]);
$error("UNIQUENESS VIOLATION: queue_c[%0d] == queue_c[%0d] == 0x%h", i, j, queue_c[i]);
return 0;
end
end
@ -78,8 +75,7 @@ module t;
continue;
end
if (assoc[i] == assoc[j]) begin
$error("UNIQUENESS VIOLATION: assoc[%0d] == assoc[%0d] == 0x%h", i, j,
assoc[i]);
$error("UNIQUENESS VIOLATION: assoc[%0d] == assoc[%0d] == 0x%h", i, j, assoc[i]);
return 0;
end
end
@ -87,12 +83,12 @@ module t;
return 1;
endfunction
endclass : UniqueMultipleArray
endclass : UniqueMultipleArray
initial begin
automatic UniqueMultipleArray a = new();
a.randomize();
assert(a.check_unique());
assert (a.check_unique());
$write("*-* All Finished *-*\n");
$finish;

30
test_regress/t/t_ext_param_func.v
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@ -4,8 +4,10 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
function automatic int align(input int a, input int b);
return a - (a % b);
@ -19,7 +21,9 @@ class Foo;
endclass
class FooParam #(parameter int param = 5);
class FooParam #(
parameter int param = 5
);
static function int mul(input int a);
return a * param;
@ -27,7 +31,9 @@ class FooParam #(parameter int param = 5);
endclass
class Base #(parameter int param = 5);
class Base #(
parameter int param = 5
);
function int get_base_param();
return param;
@ -40,14 +46,14 @@ class Base #(parameter int param = 5);
endclass
class Derived #(
parameter int a = 17,
parameter int b = 8,
parameter int c = align(a, b),
parameter int d = Base#(b)::alignUp(a),
parameter int e = Foo::mul(a, b),
parameter int f = FooParam#()::mul(a)
parameter int a = 17,
parameter int b = 8,
parameter int c = align(a, b),
parameter int d = Base#(b)::alignUp(a),
parameter int e = Foo::mul(a, b),
parameter int f = FooParam#()::mul(a)
) extends Base #(
.param (a)
.param(a)
);
function int get_third_param();
@ -68,7 +74,9 @@ class Derived #(
endclass
module t (clk);
module t (
clk
);
input clk;
Derived inst = new;

16
test_regress/t/t_param_type_dot.v
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@ -14,25 +14,27 @@ class C;
class nst;
typedef logic [2:0] S;
endclass
endclass: C
endclass
class D;
typedef logic [3:0] T;
class nst;
typedef logic [4:0] S;
endclass
endclass: D
endclass
class P#(type C);
class P #(
type C
);
localparam type C1_t = C::T;
parameter type C2_t = C::nst::S;
C1_t x = '1;
C2_t y = '1;
endclass : P
endclass
module t();
P#(C) PC_data = new();
P#(D) PD_data = new();
module t ();
P #(C) PC_data = new();
P #(D) PD_data = new();
initial begin
`checkd($bits(PC_data.x), 2);
`checkd($bits(PC_data.y), 3);

16
test_regress/t/t_param_type_dot_bad.out
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@ -1,14 +1,14 @@
%Error: t/t_param_type_dot_bad.v:13:26: Found definition of 'C' as a PARAMTYPEDTYPE but expected a scope/variable
13 | localparam type C1_t = C.T;
%Error: t/t_param_type_dot_bad.v:15:26: Found definition of 'C' as a PARAMTYPEDTYPE but expected a scope/variable
15 | localparam type C1_t = C.T;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_param_type_dot_bad.v:13:27: Expecting a data type, not a constant
13 | localparam type C1_t = C.T;
%Error: t/t_param_type_dot_bad.v:15:27: Expecting a data type, not a constant
15 | localparam type C1_t = C.T;
| ^
%Error: t/t_param_type_dot_bad.v:14:25: Found definition of 'C' as a PARAMTYPEDTYPE but expected a scope/variable
14 | parameter type C2_t = C.y;
%Error: t/t_param_type_dot_bad.v:16:25: Found definition of 'C' as a PARAMTYPEDTYPE but expected a scope/variable
16 | parameter type C2_t = C.y;
| ^
%Error: t/t_param_type_dot_bad.v:14:26: Expecting a data type, not a constant
14 | parameter type C2_t = C.y;
%Error: t/t_param_type_dot_bad.v:16:26: Expecting a data type, not a constant
16 | parameter type C2_t = C.y;
| ^
%Error: Exiting due to

10
test_regress/t/t_param_type_dot_bad.v
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@ -7,17 +7,19 @@
class C;
typedef logic [1:0] T;
static int y = 1;
endclass: C
endclass : C
class P#(type C);
class P #(
type C
);
localparam type C1_t = C.T;
parameter type C2_t = C.y;
C1_t x = '1;
C2_t y = 2;
endclass : P
module t();
P#(C) P_data = new();
module t ();
P #(C) P_data = new();
initial begin
if (P_data.x != '1) $stop;
if (P_data.y != 2) $stop;

58
test_regress/t/t_stream_unpacked_struct_port.v
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@ -16,11 +16,9 @@
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
typedef struct packed {
logic [7:0] a;
@ -29,9 +27,9 @@ module t( /*AUTOARG*/
// Unpacked struct, $bits == 40
typedef struct {
inner_t x;
inner_t x;
logic [15:0] c;
logic [7:0] d;
logic [7:0] d;
} order_t;
// Unpacked array, also $bits == 40 (so producer width OW is shared).
@ -47,19 +45,49 @@ module t( /*AUTOARG*/
// unpacked struct (needs CvtPackedToArray) and an unpacked array (does not).
order_t out_r; // right-stream {>>{}}
order_t out_l; // left-stream {<<8{}}
arr_t arr_r;
arr_t arr_l;
producer #(.W(OW)) u_r (.din(src), .dout({>>{out_r}}));
producer #(.W(OW)) u_l (.din(src), .dout({<<8{out_l}}));
producer #(.W(OW)) u_ar (.din(src), .dout({>>{arr_r}}));
producer #(.W(OW)) u_al (.din(src), .dout({<<8{arr_l}}));
arr_t arr_r;
arr_t arr_l;
producer #(
.W(OW)
) u_r (
.din(src),
.dout({>>{out_r}})
);
producer #(
.W(OW)
) u_l (
.din(src),
.dout({<<8{out_l}})
);
producer #(
.W(OW)
) u_ar (
.din(src),
.dout({>>{arr_r}})
);
producer #(
.W(OW)
) u_al (
.din(src),
.dout({<<8{arr_l}})
);
// Reference: plain packed port + separate streaming unpack assign.
wire [OW-1:0] pack_r;
wire [OW-1:0] pack_l;
order_t ref_r, ref_l;
producer #(.W(OW)) u_pr (.din(src), .dout(pack_r));
producer #(.W(OW)) u_pl (.din(src), .dout(pack_l));
producer #(
.W(OW)
) u_pr (
.din(src),
.dout(pack_r)
);
producer #(
.W(OW)
) u_pl (
.din(src),
.dout(pack_l)
);
assign ref_r = {>>{pack_r}};
assign ref_l = {<<8{pack_l}};
@ -104,7 +132,7 @@ endmodule
module producer #(
parameter int W = 1
) (
input logic [W-1:0] din,
input logic [W-1:0] din,
output logic [W-1:0] dout
);
assign dout = din;