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Add parsing of `$assert*`, `$coverage*` and `$q_*` as still unsupported.

This commit is contained in:
Wilson Snyder 2025-09-06 10:31:08 -04:00
parent 819625de61
commit 3549fd1aa0
19 changed files with 1074 additions and 431 deletions
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4
src/V3AstNodeStmt.h
View File

@ -247,8 +247,8 @@ class AstAssertCtl final : public AstNodeStmt {
VAssertDirectiveType m_directiveTypes; // Types of directives affected
public:
AstAssertCtl(FileLine* fl, VAssertCtlType ctlType, AstNodeExpr* levelp = nullptr,
AstNodeExpr* itemsp = nullptr);
AstAssertCtl(FileLine* fl, VAssertCtlType ctlType, uint32_t assertType, uint32_t directiveType,
AstNodeExpr* levelp = nullptr, AstNodeExpr* itemsp = nullptr);
AstAssertCtl(FileLine* fl, AstNodeExpr* controlTypep, AstNodeExpr* assertTypesp = nullptr,
AstNodeExpr* directiveTypep = nullptr, AstNodeExpr* levelp = nullptr,
AstNodeExpr* itemsp = nullptr);

11
src/V3AstNodes.cpp
View File

@ -1646,10 +1646,15 @@ void AstAlways::dumpJson(std::ostream& str) const {
dumpJsonStr(str, "keyword", keyword().ascii());
dumpJsonGen(str);
}
AstAssertCtl::AstAssertCtl(FileLine* fl, VAssertCtlType ctlType, AstNodeExpr*, AstNodeExpr*)
AstAssertCtl::AstAssertCtl(FileLine* fl, VAssertCtlType ctlType, uint32_t assertType,
uint32_t directiveType, AstNodeExpr*, AstNodeExpr*)
: ASTGEN_SUPER_AssertCtl(fl)
, m_ctlType{ctlType} {
controlTypep(new AstConst{fl, ctlType});
, m_ctlType{VAssertCtlType::_TO_BE_EVALUATED}
, m_assertTypes{VAssertType::INTERNAL}
, m_directiveTypes{VAssertDirectiveType::INTERNAL} {
this->controlTypep(new AstConst{fl, ctlType});
this->assertTypesp(new AstConst{fl, assertType});
this->directiveTypesp(new AstConst{fl, directiveType});
}
AstAssertCtl::AstAssertCtl(FileLine* fl, AstNodeExpr* controlTypep, AstNodeExpr* assertTypesp,
AstNodeExpr* directiveTypep, AstNodeExpr*, AstNodeExpr*)

166
src/verilog.l
View File

@ -50,11 +50,9 @@
#define ERROR_RSVD_WORD(language) \
do { \
FL; \
yylval.fl->v3warn(E_UNSUPPORTED, "Unsupported: " << language \
<< " reserved word not implemented: '" \
<< yytext << "'"); \
FL_BRK; \
} while (0)
//======================================================================
@ -259,6 +257,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$psprintf" { FL; yylval.fl->v3warn(NONSTD, "Non-standard system function '" << yytext << "';"
" suggest use standard '$sformatf' (IEEE 1800-2023 21.3.3)");
return yD_SFORMATF; }
"$q_add" { FL; ERROR_RSVD_WORD("IEEE 1364-1995"); return yaD_PLI; }
"$q_exam" { FL; ERROR_RSVD_WORD("IEEE 1364-1995"); return yaD_PLI; }
"$q_full" { FL; ERROR_RSVD_WORD("IEEE 1364-1995"); return yaD_PLI; }
"$q_initialize" { FL; ERROR_RSVD_WORD("IEEE 1364-1995"); return yaD_PLI; }
"$q_remove" { FL; ERROR_RSVD_WORD("IEEE 1364-1995"); return yaD_PLI; }
"$random" { FL; return yD_RANDOM; }
"$readmemb" { FL; return yD_READMEMB; }
"$readmemh" { FL; return yD_READMEMH; }
@ -446,14 +449,15 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"config" { FL; return yCONFIG; }
"design" { FL; return yDESIGN; }
"endconfig" { FL; return yENDCONFIG; }
"incdir" { FL; ERROR_RSVD_WORD("Verilog 2001-config lib.map"); }
"include" { FL; yylval.fl->v3warn(E_UNSUPPORTED, "Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'\n"
"incdir" { FL; ERROR_RSVD_WORD("IEEE 1800-2001-config lib.map"); FL_BRK; }
"include" { FL; yylval.fl->v3warn(E_UNSUPPORTED, "Unsupported: IEEE 1800-2001-config lib.map"
" reserved word not implemented: 'include'\n"
<< yylval.fl->warnMore() << "... Suggest unless in a lib.map file,"
" want `include instead");
FL_BRK; }
"instance" { FL; return yINSTANCE; }
"liblist" { FL; return yLIBLIST; }
"library" { FL; ERROR_RSVD_WORD("Verilog 2001-config lib.map"); }
"library" { FL; ERROR_RSVD_WORD("IEEE 1800-2001-config lib.map"); FL_BRK; }
"use" { FL; return yUSE; }
}
@ -474,6 +478,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$changing_gclk" { FL; return yD_CHANGING_GCLK; }
"$countbits" { FL; return yD_COUNTBITS; }
"$countones" { FL; return yD_COUNTONES; }
"$coverage_control" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$coverage_get" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$coverage_get_max" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$coverage_merge" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$coverage_save" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$dimensions" { FL; return yD_DIMENSIONS; }
"$error" { FL; return yD_ERROR; }
"$falling_gclk" { FL; return yD_FALLING_GCLK; }
@ -481,13 +490,16 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$fell" { FL; return yD_FELL; }
"$fell_gclk" { FL; return yD_FELL_GCLK; }
"$future_gclk" { FL; return yD_FUTURE_GCLK; }
"$get_coverage" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$high" { FL; return yD_HIGH; }
"$increment" { FL; return yD_INCREMENT; }
"$inferred_clock" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$inferred_disable" { FL; return yD_INFERRED_DISABLE; }
"$info" { FL; return yD_INFO; }
"$isunbounded" { FL; return yD_ISUNBOUNDED; }
"$isunknown" { FL; return yD_ISUNKNOWN; }
"$left" { FL; return yD_LEFT; }
"$load_coverage_db" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$low" { FL; return yD_LOW; }
"$onehot" { FL; return yD_ONEHOT; }
"$onehot0" { FL; return yD_ONEHOT0; }
@ -498,6 +510,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"$root" { FL; return yD_ROOT; }
"$rose" { FL; return yD_ROSE; }
"$rose_gclk" { FL; return yD_ROSE_GCLK; }
"$set_coverage_db_name" { FL; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; }
"$size" { FL; return yD_SIZE; }
"$stable" { FL; return yD_STABLE; }
"$stable_gclk" { FL; return yD_STABLE_GCLK; }
@ -609,6 +622,16 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* SystemVerilog 2009 */
<S09,S12,S17,S23,SAX>{
/* System Tasks */
"$assertfailoff" { FL; return yD_ASSERTFAILOFF; }
"$assertfailon" { FL; return yD_ASSERTFAILON; }
"$assertkill" { FL; return yD_ASSERTKILL; }
"$assertnonvacuouson" { FL; return yD_ASSERTNONVACUOUSON; }
"$assertoff" { FL; return yD_ASSERTOFF; }
"$asserton" { FL; return yD_ASSERTON; }
"$assertpassoff" { FL; return yD_ASSERTPASSOFF; }
"$assertpasson" { FL; return yD_ASSERTPASSON; }
"$assertvacuousoff" { FL; return yD_ASSERTVACUOUSOFF; }
/* Keywords */
"accept_on" { FL; return yACCEPT_ON; }
"checker" { FL; return yCHECKER; }
@ -638,9 +661,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<S12,S17,S23,SAX>{
/* System Tasks */
"$assertcontrol" { FL; return yD_ASSERTCTL; }
"$assertkill" { FL; return yD_ASSERTKILL; }
"$assertoff" { FL; return yD_ASSERTOFF; }
"$asserton" { FL; return yD_ASSERTON; }
/* Keywords */
"implements" { FL; return yIMPLEMENTS; }
"interconnect" { FL; return yINTERCONNECT; }
@ -665,92 +685,92 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<VA5,SAX>{
/* Generic unsupported warnings */
"1step" { FL; return y1STEP; }
"above" { ERROR_RSVD_WORD("AMS"); }
"abs" { ERROR_RSVD_WORD("AMS"); }
"absdelay" { ERROR_RSVD_WORD("AMS"); }
"abstol" { ERROR_RSVD_WORD("AMS"); }
"ac_stim" { ERROR_RSVD_WORD("AMS"); }
"access" { ERROR_RSVD_WORD("AMS"); }
"acos" { ERROR_RSVD_WORD("AMS"); }
"acosh" { ERROR_RSVD_WORD("AMS"); }
"aliasparam" { ERROR_RSVD_WORD("AMS"); }
"analog" { ERROR_RSVD_WORD("AMS"); }
"analysis" { ERROR_RSVD_WORD("AMS"); }
"above" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"abs" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"absdelay" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"abstol" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ac_stim" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"access" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"acos" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"acosh" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"aliasparam" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"analog" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"analysis" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"asin" { FL; return yD_ASIN; }
"asinh" { FL; return yD_ASINH; }
"assert" { ERROR_RSVD_WORD("AMS"); }
"assert" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"atan" { FL; return yD_ATAN; }
"atan2" { FL; return yD_ATAN2; }
"atanh" { FL; return yD_ATANH; }
"branch" { ERROR_RSVD_WORD("AMS"); }
"branch" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ceil" { FL; return yD_CEIL; }
"connect" { ERROR_RSVD_WORD("AMS"); }
"connectmodule" { ERROR_RSVD_WORD("AMS"); }
"connectrules" { ERROR_RSVD_WORD("AMS"); }
"continuous" { ERROR_RSVD_WORD("AMS"); }
"connect" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"connectmodule" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"connectrules" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"continuous" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"cos" { FL; return yD_COS; }
"cosh" { FL; return yD_COSH; }
"cross" { ERROR_RSVD_WORD("AMS"); }
"ddt" { ERROR_RSVD_WORD("AMS"); }
"ddt_nature" { ERROR_RSVD_WORD("AMS"); }
"ddx" { ERROR_RSVD_WORD("AMS"); }
"discipline" { ERROR_RSVD_WORD("AMS"); }
"discrete" { ERROR_RSVD_WORD("AMS"); }
"domain" { ERROR_RSVD_WORD("AMS"); }
"driver_update" { ERROR_RSVD_WORD("AMS"); }
"endconnectrules" { ERROR_RSVD_WORD("AMS"); }
"enddiscipline" { ERROR_RSVD_WORD("AMS"); }
"endnature" { ERROR_RSVD_WORD("AMS"); }
"endparamset" { ERROR_RSVD_WORD("AMS"); }
"exclude" { ERROR_RSVD_WORD("AMS"); }
"cross" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ddt" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ddt_nature" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ddx" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"discipline" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"discrete" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"domain" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"driver_update" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"endconnectrules" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"enddiscipline" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"endnature" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"endparamset" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"exclude" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"exp" { FL; return yD_EXP; }
"final_step" { ERROR_RSVD_WORD("AMS"); }
"flicker_noise" { ERROR_RSVD_WORD("AMS"); }
"final_step" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"flicker_noise" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"floor" { FL; return yD_FLOOR; }
"flow" { ERROR_RSVD_WORD("AMS"); }
"from" { ERROR_RSVD_WORD("AMS"); }
"ground" { ERROR_RSVD_WORD("AMS"); }
"flow" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"from" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ground" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"hypot" { FL; return yD_HYPOT; }
"idt" { ERROR_RSVD_WORD("AMS"); }
"idt_nature" { ERROR_RSVD_WORD("AMS"); }
"idtmod" { ERROR_RSVD_WORD("AMS"); }
"inf" { ERROR_RSVD_WORD("AMS"); }
"initial_step" { ERROR_RSVD_WORD("AMS"); }
"laplace_nd" { ERROR_RSVD_WORD("AMS"); }
"laplace_np" { ERROR_RSVD_WORD("AMS"); }
"laplace_zd" { ERROR_RSVD_WORD("AMS"); }
"laplace_zp" { ERROR_RSVD_WORD("AMS"); }
"last_crossing" { ERROR_RSVD_WORD("AMS"); }
"limexp" { ERROR_RSVD_WORD("AMS"); }
"idt" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"idt_nature" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"idtmod" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"inf" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"initial_step" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"laplace_nd" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"laplace_np" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"laplace_zd" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"laplace_zp" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"last_crossing" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"limexp" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"ln" { FL; return yD_LN; }
"log" { FL; return yD_LOG10; }
"max" { ERROR_RSVD_WORD("AMS"); }
"merged" { ERROR_RSVD_WORD("AMS"); }
"min" { ERROR_RSVD_WORD("AMS"); }
"nature" { ERROR_RSVD_WORD("AMS"); }
"net_resolution" { ERROR_RSVD_WORD("AMS"); }
"noise_table" { ERROR_RSVD_WORD("AMS"); }
"paramset" { ERROR_RSVD_WORD("AMS"); }
"potential" { ERROR_RSVD_WORD("AMS"); }
"max" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"merged" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"min" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"nature" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"net_resolution" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"noise_table" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"paramset" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"potential" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"pow" { FL; return yD_POW; }
"resolveto" { ERROR_RSVD_WORD("AMS"); }
"resolveto" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"sin" { FL; return yD_SIN; }
"sinh" { FL; return yD_SINH; }
"slew" { ERROR_RSVD_WORD("AMS"); }
"split" { ERROR_RSVD_WORD("AMS"); }
"slew" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"split" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"sqrt" { FL; return yD_SQRT; }
"string" { FL; return ySTRING; }
"tan" { FL; return yD_TAN; }
"tanh" { FL; return yD_TANH; }
"timer" { ERROR_RSVD_WORD("AMS"); }
"transition" { ERROR_RSVD_WORD("AMS"); }
"units" { ERROR_RSVD_WORD("AMS"); }
"white_noise" { ERROR_RSVD_WORD("AMS"); }
"timer" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"transition" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"units" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"white_noise" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"wreal" { FL; return yWREAL; }
"zi_nd" { ERROR_RSVD_WORD("AMS"); }
"zi_np" { ERROR_RSVD_WORD("AMS"); }
"zi_zd" { ERROR_RSVD_WORD("AMS"); }
"zi_zp" { ERROR_RSVD_WORD("AMS"); }
"zi_nd" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"zi_np" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"zi_zd" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
"zi_zp" { FL; ERROR_RSVD_WORD("AMS"); FL_BRK; }
}
/************************************************************************/

51
src/verilog.y
View File

@ -530,13 +530,13 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<strp> yaSTRING "STRING"
%token<strp> yaSTRING__IGNORE "STRING-ignored" // Used when expr:string not allowed
// IEEE: edge_descriptor
%token<nump> yaEDGEDESC "EDGE DESCRIPTOR"
%token<nump> yaEDGEDESC "EDGE DESCRIPTOR"
%token<fl> yaTIMINGSPEC "TIMING SPEC ELEMENT"
%token<fl> ygenSTRENGTH "STRENGTH keyword (strong1/etc)"
%token<strp> yaTABLE_FIELD "UDP table field"
%token<strp> yaTABLE_FIELD "UDP table field"
%token<fl> yaTABLE_LRSEP ":"
%token<fl> yaTABLE_LINEEND "UDP table line end"
@ -903,9 +903,15 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yD_ASIN "$asin"
%token<fl> yD_ASINH "$asinh"
%token<fl> yD_ASSERTCTL "$assertcontrol"
%token<fl> yD_ASSERTFAILOFF "$assertfailoff"
%token<fl> yD_ASSERTFAILON "$assertfailon"
%token<fl> yD_ASSERTKILL "$assertkill"
%token<fl> yD_ASSERTNONVACUOUSON "$assertnonvacuouson"
%token<fl> yD_ASSERTOFF "$assertoff"
%token<fl> yD_ASSERTON "$asserton"
%token<fl> yD_ASSERTPASSOFF "$assertpassoff"
%token<fl> yD_ASSERTPASSON "$assertpasson"
%token<fl> yD_ASSERTVACUOUSOFF "$assertvacuousoff"
%token<fl> yD_ATAN "$atan"
%token<fl> yD_ATAN2 "$atan2"
%token<fl> yD_ATANH "$atanh"
@ -4483,15 +4489,33 @@ system_t_call<nodeStmtp>: // IEEE: system_tf_call (as task)
| yD_ASSERTCTL '(' expr ',' exprE ',' exprE ')' { $$ = new AstAssertCtl{$1, $3, $5, $7}; }
| yD_ASSERTCTL '(' expr ',' exprE ',' exprE ',' exprE ')' { $$ = new AstAssertCtl{$1, $3, $5, $7, $9}; }
| yD_ASSERTCTL '(' expr ',' exprE ',' exprE ',' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, $3, $5, $7, $9, $11}; }
| yD_ASSERTKILL parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL}; }
| yD_ASSERTKILL '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, $3}; }
| yD_ASSERTKILL '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, $3, $5}; }
| yD_ASSERTOFF parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF}; }
| yD_ASSERTOFF '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, $3}; }
| yD_ASSERTOFF '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, $3, $5}; }
| yD_ASSERTON parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::ON}; }
| yD_ASSERTON '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, $3}; }
| yD_ASSERTON '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, $3, $5}; }
| yD_ASSERTFAILOFF '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::FAIL_OFF, 31, 7, $3}; }
| yD_ASSERTFAILOFF '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::FAIL_OFF, 31, 7, $3, $5}; }
| yD_ASSERTFAILOFF parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::FAIL_OFF, 31, 7}; }
| yD_ASSERTFAILON '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::FAIL_ON, 31, 7, $3}; }
| yD_ASSERTFAILON '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::FAIL_ON, 31, 7, $3, $5}; }
| yD_ASSERTFAILON parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::FAIL_ON, 31, 7}; }
| yD_ASSERTKILL '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, 15, 7, $3}; }
| yD_ASSERTKILL '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, 15, 7, $3, $5}; }
| yD_ASSERTKILL parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, 15, 7}; }
| yD_ASSERTNONVACUOUSON '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::NONVACUOUS_ON, 31, 7, $3}; }
| yD_ASSERTNONVACUOUSON '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::NONVACUOUS_ON, 31, 7, $3, $5}; }
| yD_ASSERTNONVACUOUSON parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::NONVACUOUS_ON, 31, 7}; }
| yD_ASSERTOFF '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, 15, 7, $3}; }
| yD_ASSERTOFF '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, 15, 7, $3, $5}; }
| yD_ASSERTOFF parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, 15, 7}; }
| yD_ASSERTON '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, 15, 7, $3}; }
| yD_ASSERTON '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, 15, 7, $3, $5}; }
| yD_ASSERTON parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, 15, 7}; }
| yD_ASSERTPASSOFF '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::PASS_OFF, 31, 7, $3}; }
| yD_ASSERTPASSOFF '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::PASS_OFF, 31, 7, $3, $5}; }
| yD_ASSERTPASSOFF parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::PASS_OFF, 31, 7}; }
| yD_ASSERTPASSON '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::PASS_ON, 31, 7, $3}; }
| yD_ASSERTPASSON '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::PASS_ON, 31, 7, $3, $5}; }
| yD_ASSERTPASSON parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::PASS_ON, 31, 7}; }
| yD_ASSERTVACUOUSOFF '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::VACUOUS_OFF, 31, 7, $3}; }
| yD_ASSERTVACUOUSOFF '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::VACUOUS_OFF, 31, 7, $3, $5}; }
| yD_ASSERTVACUOUSOFF parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::VACUOUS_OFF, 31, 7}; }
//
| yD_MONITOROFF parenE { $$ = new AstMonitorOff{$1, true}; }
| yD_MONITORON parenE { $$ = new AstMonitorOff{$1, false}; }
@ -6654,9 +6678,10 @@ sequence_declarationBody<nodep>: // IEEE: part of sequence_declaration
property_spec<propSpecp>: // IEEE: property_spec
//UNSUP: This rule has been super-specialized to what is supported now
//UNSUP remove below
'@' '(' senitemEdge ')' yDISABLE yIFF '(' expr ')' pexpr
'@' '(' senitem ')' yDISABLE yIFF '(' expr ')' pexpr
{ $$ = new AstPropSpec{$1, $3, $8, $10}; }
| '@' '(' senitemEdge ')' pexpr { $$ = new AstPropSpec{$1, $3, nullptr, $5}; }
| '@' '(' senitem ')' pexpr
{ $$ = new AstPropSpec{$1, $3, nullptr, $5}; }
// // Disable applied after the event occurs,
// // so no existing AST can represent this
| yDISABLE yIFF '(' expr ')' '@' '(' senitemEdge ')' pexpr

66
test_regress/t/t_assert_ctl_arg.v
View File

@ -25,9 +25,9 @@ module t (/*AUTOARG*/
);
input clk;
let ON = 3;
let OFF = 4;
let KILL = 5;
let On = 3;
let Off = 4;
let Kill = 5;
let CONCURRENT = 1;
let SIMPLE_IMMEDIATE = 2;
@ -44,24 +44,24 @@ module t (/*AUTOARG*/
initial begin
// simple immediate
$assertcontrol(OFF, ALL_TYPES);
$assertcontrol(ON, SIMPLE_IMMEDIATE);
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(OFF, SIMPLE_IMMEDIATE);
$assertcontrol(Off, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS
// observed deferred immediate
$assertcontrol(OFF, ALL_TYPES);
$assertcontrol(ON, OBSERVED_DEFERRED_IMMEDIATE);
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(OFF, OBSERVED_DEFERRED_IMMEDIATE);
$assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
// final deferred immediate
$assertcontrol(OFF, ALL_TYPES);
$assertcontrol(ON, FINAL_DEFERRED_IMMEDIATE);
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(OFF, FINAL_DEFERRED_IMMEDIATE);
$assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
// on, off, kill test
@ -72,54 +72,54 @@ module t (/*AUTOARG*/
$assertkill;
`RUN_ALL_ASSERTS;
$assertcontrol(ON, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE);
$assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(ON, FINAL_DEFERRED_IMMEDIATE);
$assertcontrol(On, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE);
$assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, FINAL_DEFERRED_IMMEDIATE);
$assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, SIMPLE_IMMEDIATE);
$assertcontrol(Off, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(ON, SIMPLE_IMMEDIATE);
$assertcontrol(On, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, ALL_TYPES);
$assertcontrol(Off, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(ON, ALL_TYPES);
$assertcontrol(On, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(KILL, ALL_TYPES);
$assertcontrol(Kill, ALL_TYPES);
`RUN_ALL_ASSERTS;
// directive_type test
$assertoff;
$assertcontrol(ON, ALL_TYPES, ASSERT);
$assertcontrol(On, ALL_TYPES, ASSERT);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, ALL_TYPES, ASSERT);
$assertcontrol(ON, ALL_TYPES, COVER);
$assertcontrol(Off, ALL_TYPES, ASSERT);
$assertcontrol(On, ALL_TYPES, COVER);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, ALL_TYPES, COVER);
$assertcontrol(ON, ALL_TYPES, ASSUME);
$assertcontrol(Off, ALL_TYPES, COVER);
$assertcontrol(On, ALL_TYPES, ASSUME);
`RUN_ALL_ASSERTS;
$assertcontrol(OFF, ALL_TYPES, ASSUME);
$assertcontrol(ON, ALL_TYPES, ASSERT|COVER);
$assertcontrol(Off, ALL_TYPES, ASSUME);
$assertcontrol(On, ALL_TYPES, ASSERT|COVER);
`RUN_ALL_ASSERTS;
$assertcontrol(ON, ALL_TYPES, ASSUME);
$assertcontrol(On, ALL_TYPES, ASSUME);
`RUN_ALL_ASSERTS;
$assertoff;
`RUN_ALL_ASSERTS;
$assertcontrol(ON, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME);
$assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME);
`RUN_ALL_ASSERTS;
$assertoff;
// concurrent test
#10;
$display("Disabling concurrent asserts, time: %g", $time);
$assertcontrol(ON, ALL_TYPES);
$assertcontrol(OFF, CONCURRENT);
$assertcontrol(On, ALL_TYPES);
$assertcontrol(Off, CONCURRENT);
#10;
$display("Enabling concurrent asserts, time: %g", $time);
$assertcontrol(ON, CONCURRENT);
$assertcontrol(On, CONCURRENT);
$write("*-* All Finished *-*\n");
$finish;

8
test_regress/t/t_assert_ctl_type_bad.out Normal file
View File

@ -0,0 +1,8 @@
%Error: t/t_assert_ctl_type_bad.v:9:5: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
9 | $assertcontrol(0);
| ^~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assert_ctl_type_bad.v:10:5: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
10 | $assertcontrol(100);
| ^~~~~~~~~~~~~~
%Error: Exiting due to

16
test_regress/t/t_assert_ctl_type_bad.py Executable file
View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename)
test.passes()

12
test_regress/t/t_assert_ctl_type_bad.v Executable file
View File

@ -0,0 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
$assertcontrol(0);
$assertcontrol(100);
end
endmodule

135
test_regress/t/t_assert_ctl_unsup.out
View File

@ -1,58 +1,123 @@
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:18:7: Unsupported: non-constant assert assertion-type expression
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported: non-constant assert assertion-type expression
: ... note: In instance 't.unsupported_ctl_type'
18 | $assertcontrol(1, a);
25 | $assertcontrol(Lock, a);
| ^~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:19:7: Unsupported assertcontrol control_type
19 | $assertcontrol(2);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:7: Unsupported assertcontrol control_type
27 | $assertcontrol(Unlock);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:20:7: Unsupported assertcontrol control_type
20 | $assertcontrol(6);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:7: Unsupported assertcontrol control_type
29 | $assertcontrol(PassOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:21:7: Unsupported assertcontrol control_type
21 | $assertcontrol(7);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
30 | $assertpasson;
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
31 | $assertpasson(a);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
32 | $assertpasson(a, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:7: Unsupported assertcontrol control_type
34 | $assertcontrol(PassOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:22:7: Unsupported assertcontrol control_type
22 | $assertcontrol(8);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
35 | $assertpassoff;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:23:7: Unsupported assertcontrol control_type
23 | $assertcontrol(9);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
36 | $assertpassoff(a);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:24:7: Unsupported assertcontrol control_type
24 | $assertcontrol(10);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
37 | $assertpassoff(a, t);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported assertcontrol control_type
25 | $assertcontrol(11);
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:7: Unsupported assertcontrol control_type
39 | $assertcontrol(FailOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: non-const assert control type expression
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
40 | $assertfailon;
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
41 | $assertfailon(a);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
42 | $assertfailon(a, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:7: Unsupported assertcontrol control_type
44 | $assertcontrol(FailOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
45 | $assertfailoff;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
46 | $assertfailoff(a);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
47 | $assertfailoff(a, t);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:7: Unsupported assertcontrol control_type
49 | $assertcontrol(NonvacuousOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
50 | $assertnonvacuouson;
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
51 | $assertnonvacuouson(a);
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
52 | $assertnonvacuouson(a, t);
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:7: Unsupported assertcontrol control_type
54 | $assertcontrol(VacuousOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
55 | $assertvacuousoff;
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
56 | $assertvacuousoff(a);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:7: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
57 | $assertvacuousoff(a, t);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:7: Unsupported: non-const assert control type expression
: ... note: In instance 't.unsupported_ctl_type_expr'
32 | $assertcontrol(ctl_type);
64 | $assertcontrol(ctl_type);
| ^~~~~~~~~~~~~~
%Error: t/t_assert_ctl_unsup.v:38:7: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
38 | $assertcontrol(0);
| ^~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assert_ctl_unsup.v:39:7: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
39 | $assertcontrol(100);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:68:10: Unsupported: assertcontrols in classes or interfaces
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:10: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class'
68 | $asserton;
93 | $asserton;
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:74:10: Unsupported: assertcontrols in classes or interfaces
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:10: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class'
74 | $assertoff;
99 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:147:7: Unsupported: assertcontrols in classes or interfaces
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface'
147 | $assertoff;
172 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:113:7: Unsupported: assertcontrols in classes or interfaces
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class'
113 | $assertoff;
138 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:120:7: Unsupported: assertcontrols in classes or interfaces
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class'
120 | $asserton;
145 | $asserton;
| ^~~~~~~~~
%Error: Exiting due to

57
test_regress/t/t_assert_ctl_unsup.v
View File

@ -7,7 +7,6 @@
module t(input logic clk);
unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2);
unsupported_ctl_type_expr unsupported_ctl_type_expr();
bad_assertcontrol_ctl_type bad_assertcontrol_ctl_type();
assert_class assert_class();
assert_iface assert_iface();
assert_iface_class assert_iface_class();
@ -15,14 +14,47 @@ endmodule
module unsupported_ctl_type(input int a);
initial begin
$assertcontrol(1, a);
$assertcontrol(2);
$assertcontrol(6);
$assertcontrol(7);
$assertcontrol(8);
$assertcontrol(9);
$assertcontrol(10);
$assertcontrol(11);
let Lock = 1;
let Unlock = 2;
let PassOn = 6;
let PassOff = 7;
let FailOn = 8;
let FailOff = 9;
let NonvacuousOn = 10;
let VacuousOff = 11;
$assertcontrol(Lock, a);
$assertcontrol(Unlock);
$assertcontrol(PassOn);
$assertpasson;
$assertpasson(a);
$assertpasson(a, t);
$assertcontrol(PassOff);
$assertpassoff;
$assertpassoff(a);
$assertpassoff(a, t);
$assertcontrol(FailOn);
$assertfailon;
$assertfailon(a);
$assertfailon(a, t);
$assertcontrol(FailOff);
$assertfailoff;
$assertfailoff(a);
$assertfailoff(a, t);
$assertcontrol(NonvacuousOn);
$assertnonvacuouson;
$assertnonvacuouson(a);
$assertnonvacuouson(a, t);
$assertcontrol(VacuousOff);
$assertvacuousoff;
$assertvacuousoff(a);
$assertvacuousoff(a, t);
end
endmodule
@ -33,13 +65,6 @@ module unsupported_ctl_type_expr;
end
endmodule
module bad_assertcontrol_ctl_type;
initial begin
$assertcontrol(0);
$assertcontrol(100);
end
endmodule
module assert_class;
virtual class AssertCtl;
pure virtual function void virtual_assert_ctl();

2
test_regress/t/t_config_include_bad.out
View File

@ -1,4 +1,4 @@
%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
7 | include "meant_to_tick_include.v"
| ^~~~~~~

30
test_regress/t/t_config_libmap.out
View File

@ -1,4 +1,4 @@
%Error-UNSUPPORTED: t/t_config_libmap.map:9:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
%Error-UNSUPPORTED: t/t_config_libmap.map:9:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
9 | include ./t_config_libmap_inc.map
| ^~~~~~~
@ -7,23 +7,25 @@
9 | include ./t_config_libmap_inc.map
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_config_libmap.map:11:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
%Error-UNSUPPORTED: t/t_config_libmap.map:11:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library'
11 | library rtllib *.v;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:12:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
| ^~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:12:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library'
12 | library rtllib2 *.v, *.sv;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:13:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
| ^~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:13:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library'
13 | library rtllib3 *.v -incdir *.vh;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:13:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
%Error-UNSUPPORTED: t/t_config_libmap.map:14:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
| ^~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:13:22: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'incdir'
13 | library rtllib3 *.v -incdir *.vh;
| ^~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:14:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library'
14 | library rtllib4 *.v -incdir *.vh, *.svh;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:14:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
| ^~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:14:22: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'incdir'
14 | library rtllib4 *.v -incdir *.vh, *.svh;
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
| ^~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library'
17 | library gatelib .
| ^~~~~~~~~~~~~~
| ^~~~~~~
%Error: Exiting due to

26
test_regress/t/t_cover_sys_unsup.out Normal file
View File

@ -0,0 +1,26 @@
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:18:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_control'
18 | i = $coverage_control(0, 23, 10, t);
| ^~~~~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:21:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_get'
21 | i = $coverage_get(23, 10, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:24:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_get_max'
24 | i = $coverage_get_max(23, 10, t);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:27:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$get_coverage'
27 | r = $get_coverage();
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:29:5: Unsupported: IEEE 1800-2005 reserved word not implemented: '$set_coverage_db_name'
29 | $set_coverage_db_name("filename");
| ^~~~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:31:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_save'
31 | i = $coverage_save(coverage_type, "filename");
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:34:5: Unsupported: IEEE 1800-2005 reserved word not implemented: '$load_coverage_db'
34 | $load_coverage_db("filename");
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:36:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_merge'
36 | i = $coverage_merge(coverage_type, "filename");
| ^~~~~~~~~~~~~~~
%Error: Exiting due to

16
test_regress/t/t_cover_sys_unsup.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
test.passes()

42
test_regress/t/t_cover_sys_unsup.v Normal file
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@ -0,0 +1,42 @@
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
//
// Simple bi-directional alias test.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
real r;
int i;
initial begin
// control_constant = `SV_COV_START, `SV_COV_STOP, `SV_COV_RESET, `SV_COV_CHECK
// coverage_type = `SV_COV_ASSERTION, `SV_COV_FSM_STATE, `SV_COV_STATEMENT,`SV_COV_TOGGLE
// scope_def = [`SV_COV_MODULE, "unique module def name"], [`SV_COV_HIER, "module name"],
// [`SV_COV_MODULE, instance_name], [`SV_COV_HIER, instance_name]
i = $coverage_control(`SV_COV_START, `SV_COV_TOGGLE, `SV_COV_MODULE, t);
// returns `SV_COV_OK, `SV_COV_ERROR, `SV_COV_NOCOV, `SV_COV_PARTIAL
i = $coverage_get(`SV_COV_TOGGLE, `SV_COV_MODULE, t);
// returns number or `SC_COV_OVERFLOW, `SC_COV_ERROR, `SV_COV_NOCOV
i = $coverage_get_max(`SV_COV_TOGGLE, `SV_COV_MODULE, t);
// returns number or `SC_COV_OVERFLOW, `SC_COV_ERROR, `SV_COV_NOCOV
r = $get_coverage();
$set_coverage_db_name("filename");
i = $coverage_save(coverage_type, "filename");
// returns `SV_COV_OK, `SC_COV_NOCOV, `SC_COV_ERROR
$load_coverage_db("filename");
i = $coverage_merge(coverage_type, "filename");
// returns `SV_COV_OK, `SC_COV_NOCOV, `SC_COV_ERROR
$finish;
end
endmodule

500
test_regress/t/t_dump_json.out
View File

@ -488,34 +488,52 @@
"lhsp": [
{"type":"PARSEREF","name":"out","addr":"(XH)","loc":"e,83:7,83:10","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],"timingControlp": []},
{"type":"ASSERTCTL","name":"","addr":"(YH)","loc":"e,86:7,86:17","ctlType":"$assertoff",
{"type":"ASSERTCTL","name":"","addr":"(YH)","loc":"e,86:7,86:17","ctlType":"",
"controlTypep": [
{"type":"CONST","name":"32'h4","addr":"(ZH)","loc":"e,86:7,86:17","dtypep":"(OC)"}
],"assertTypesp": [],"directiveTypesp": []},
{"type":"ASSERTCTL","name":"","addr":"(AI)","loc":"e,87:7,87:18","ctlType":"$assertkill",
"controlTypep": [
{"type":"CONST","name":"32'h5","addr":"(BI)","loc":"e,87:7,87:18","dtypep":"(OC)"}
],"assertTypesp": [],"directiveTypesp": []},
{"type":"ASSERT","name":"","addr":"(CI)","loc":"e,88:7,88:13","type":"[SIMPLE_IMMEDIATE]",
"propp": [
{"type":"CONST","name":"?32?sh0","addr":"(DI)","loc":"e,88:14,88:15","dtypep":"(N)"}
],"sentreep": [],"failsp": [],"passsp": []},
{"type":"ASSERTCTL","name":"","addr":"(EI)","loc":"e,89:7,89:16","ctlType":"$asserton",
"controlTypep": [
{"type":"CONST","name":"32'h3","addr":"(FI)","loc":"e,89:7,89:16","dtypep":"(OC)"}
],"assertTypesp": [],"directiveTypesp": []},
{"type":"ASSERTCTL","name":"","addr":"(GI)","loc":"e,90:7,90:21","ctlType":"",
"controlTypep": [
{"type":"CONST","name":"?32?sh3","addr":"(HI)","loc":"e,90:22,90:23","dtypep":"(SD)"}
],
"assertTypesp": [
{"type":"CONST","name":"?32?sh8","addr":"(II)","loc":"e,90:25,90:26","dtypep":"(LF)"}
{"type":"CONST","name":"32'hf","addr":"(AI)","loc":"e,86:7,86:17","dtypep":"(OC)"}
],
"directiveTypesp": [
{"type":"CONST","name":"32'h7","addr":"(BI)","loc":"e,86:7,86:17","dtypep":"(OC)"}
]},
{"type":"ASSERTCTL","name":"","addr":"(CI)","loc":"e,87:7,87:18","ctlType":"",
"controlTypep": [
{"type":"CONST","name":"32'h5","addr":"(DI)","loc":"e,87:7,87:18","dtypep":"(OC)"}
],
"assertTypesp": [
{"type":"CONST","name":"32'hf","addr":"(EI)","loc":"e,87:7,87:18","dtypep":"(OC)"}
],
"directiveTypesp": [
{"type":"CONST","name":"32'h7","addr":"(FI)","loc":"e,87:7,87:18","dtypep":"(OC)"}
]},
{"type":"ASSERT","name":"","addr":"(GI)","loc":"e,88:7,88:13","type":"[SIMPLE_IMMEDIATE]",
"propp": [
{"type":"CONST","name":"?32?sh0","addr":"(HI)","loc":"e,88:14,88:15","dtypep":"(N)"}
],"sentreep": [],"failsp": [],"passsp": []},
{"type":"ASSERTCTL","name":"","addr":"(II)","loc":"e,89:7,89:16","ctlType":"",
"controlTypep": [
{"type":"CONST","name":"32'h3","addr":"(JI)","loc":"e,89:7,89:16","dtypep":"(OC)"}
],
"assertTypesp": [
{"type":"CONST","name":"32'hf","addr":"(KI)","loc":"e,89:7,89:16","dtypep":"(OC)"}
],
"directiveTypesp": [
{"type":"CONST","name":"32'h7","addr":"(LI)","loc":"e,89:7,89:16","dtypep":"(OC)"}
]},
{"type":"ASSERTCTL","name":"","addr":"(MI)","loc":"e,90:7,90:21","ctlType":"",
"controlTypep": [
{"type":"CONST","name":"?32?sh3","addr":"(NI)","loc":"e,90:22,90:23","dtypep":"(SD)"}
],
"assertTypesp": [
{"type":"CONST","name":"?32?sh8","addr":"(OI)","loc":"e,90:25,90:26","dtypep":"(LF)"}
],"directiveTypesp": []},
{"type":"BEGIN","name":"blk","addr":"(JI)","loc":"e,91:15,91:18","generate":false,"genfor":false,"implied":false,"needProcess":false,"unnamed":false,"genforp": [],
{"type":"BEGIN","name":"blk","addr":"(PI)","loc":"e,91:15,91:18","generate":false,"genfor":false,"implied":false,"needProcess":false,"unnamed":false,"genforp": [],
"stmtsp": [
{"type":"DISABLE","name":"","addr":"(KI)","loc":"e,92:10,92:17",
{"type":"DISABLE","name":"","addr":"(QI)","loc":"e,92:10,92:17",
"targetRefp": [
{"type":"PARSEREF","name":"blk","addr":"(LI)","loc":"e,92:18,92:21","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"blk","addr":"(RI)","loc":"e,92:18,92:21","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
]}
]}
]}
@ -524,550 +542,550 @@
]},
{"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","level":3,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"PACKAGEIMPORT","name":"*","addr":"(MI)","loc":"d,31:9,31:12","packagep":"(F)"}
{"type":"PACKAGEIMPORT","name":"*","addr":"(SI)","loc":"d,31:9,31:12","packagep":"(F)"}
]},
{"type":"PACKAGE","name":"std","addr":"(F)","loc":"d,31:9,31:12","origName":"std","level":4,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"CLASS","name":"mailbox","addr":"(NI)","loc":"d,32:4,32:9","isExtended":false,"isInterfaceClass":false,"isVirtual":false,"origName":"mailbox","level":5,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","classOrPackagep":"UNLINKED","inlinesp": [],
{"type":"CLASS","name":"mailbox","addr":"(TI)","loc":"d,32:4,32:9","isExtended":false,"isInterfaceClass":false,"isVirtual":false,"origName":"mailbox","level":5,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","classOrPackagep":"UNLINKED","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"T","addr":"(OI)","loc":"d,32:25,32:26","dtypep":"UNLINKED","origName":"T","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"GPARAM","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"VAR","name":"T","addr":"(UI)","loc":"d,32:25,32:26","dtypep":"UNLINKED","origName":"T","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"GPARAM","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"PARSETYPEDTYPE","name":"","addr":"(PI)","loc":"d,32:20,32:24","dtypep":"UNLINKED","generic":false}
{"type":"PARSETYPEDTYPE","name":"","addr":"(VI)","loc":"d,32:20,32:24","dtypep":"UNLINKED","generic":false}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"TYPEDEFFWD","name":"T","addr":"(QI)","loc":"d,32:25,32:26","fwdType":"none"},
{"type":"VAR","name":"m_bound","addr":"(RI)","loc":"d,33:21,33:28","dtypep":"UNLINKED","origName":"m_bound","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"TYPEDEFFWD","name":"T","addr":"(WI)","loc":"d,32:25,32:26","fwdType":"none"},
{"type":"VAR","name":"m_bound","addr":"(XI)","loc":"d,33:21,33:28","dtypep":"UNLINKED","origName":"m_bound","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"int","addr":"(SI)","loc":"d,33:17,33:20","dtypep":"(SI)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(YI)","loc":"d,33:17,33:20","dtypep":"(YI)","keyword":"int","range":"31:0","generic":false,"rangep": []}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"m_queue","addr":"(TI)","loc":"d,34:19,34:26","dtypep":"UNLINKED","origName":"m_queue","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"VAR","name":"m_queue","addr":"(ZI)","loc":"d,34:19,34:26","dtypep":"UNLINKED","origName":"m_queue","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BRACKETARRAYDTYPE","name":"","addr":"(UI)","loc":"d,34:26,34:27","dtypep":"UNLINKED","generic":false,
{"type":"BRACKETARRAYDTYPE","name":"","addr":"(AJ)","loc":"d,34:26,34:27","dtypep":"UNLINKED","generic":false,
"childDTypep": [
{"type":"REFDTYPE","name":"T","addr":"(VI)","loc":"d,34:17,34:18","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}
{"type":"REFDTYPE","name":"T","addr":"(BJ)","loc":"d,34:17,34:18","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}
],
"elementsp": [
{"type":"UNBOUNDED","name":"","addr":"(WI)","loc":"d,34:27,34:28","dtypep":"(XI)"}
{"type":"UNBOUNDED","name":"","addr":"(CJ)","loc":"d,34:27,34:28","dtypep":"(DJ)"}
]}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"FUNC","name":"new","addr":"(YI)","loc":"d,36:16,36:19","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [],
{"type":"FUNC","name":"new","addr":"(EJ)","loc":"d,36:16,36:19","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"bound","addr":"(ZI)","loc":"d,36:24,36:29","dtypep":"UNLINKED","origName":"bound","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"VAR","name":"bound","addr":"(FJ)","loc":"d,36:24,36:29","dtypep":"UNLINKED","origName":"bound","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"int","addr":"(AJ)","loc":"d,36:20,36:23","dtypep":"(AJ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(GJ)","loc":"d,36:20,36:23","dtypep":"(GJ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
],"delayp": [],
"valuep": [
{"type":"CONST","name":"?32?sh0","addr":"(BJ)","loc":"d,36:32,36:33","dtypep":"(N)"}
{"type":"CONST","name":"?32?sh0","addr":"(HJ)","loc":"d,36:32,36:33","dtypep":"(N)"}
],"attrsp": []},
{"type":"ASSIGN","name":"","addr":"(CJ)","loc":"d,37:18,37:19","dtypep":"UNLINKED",
{"type":"ASSIGN","name":"","addr":"(IJ)","loc":"d,37:18,37:19","dtypep":"UNLINKED",
"rhsp": [
{"type":"PARSEREF","name":"bound","addr":"(DJ)","loc":"d,37:20,37:25","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"bound","addr":"(JJ)","loc":"d,37:20,37:25","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],
"lhsp": [
{"type":"PARSEREF","name":"m_bound","addr":"(EJ)","loc":"d,37:10,37:17","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"m_bound","addr":"(KJ)","loc":"d,37:10,37:17","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],"timingControlp": []}
],"scopeNamep": []},
{"type":"FUNC","name":"num","addr":"(FJ)","loc":"d,40:20,40:23","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"num",
{"type":"FUNC","name":"num","addr":"(LJ)","loc":"d,40:20,40:23","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"num",
"fvarp": [
{"type":"BASICDTYPE","name":"int","addr":"(GJ)","loc":"d,40:16,40:19","dtypep":"(GJ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(MJ)","loc":"d,40:16,40:19","dtypep":"(MJ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"RETURN","name":"","addr":"(HJ)","loc":"d,41:10,41:16",
{"type":"RETURN","name":"","addr":"(NJ)","loc":"d,41:10,41:16",
"lhsp": [
{"type":"DOT","name":"","addr":"(IJ)","loc":"d,41:24,41:25","dtypep":"UNLINKED","colon":false,
{"type":"DOT","name":"","addr":"(OJ)","loc":"d,41:24,41:25","dtypep":"UNLINKED","colon":false,
"lhsp": [
{"type":"PARSEREF","name":"m_queue","addr":"(JJ)","loc":"d,41:17,41:24","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"m_queue","addr":"(PJ)","loc":"d,41:17,41:24","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],
"rhsp": [
{"type":"FUNCREF","name":"size","addr":"(KJ)","loc":"d,41:25,41:29","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []}
{"type":"FUNCREF","name":"size","addr":"(QJ)","loc":"d,41:25,41:29","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []}
]}
]}
],"scopeNamep": []},
{"type":"TASK","name":"put","addr":"(LJ)","loc":"d,44:12,44:15","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"put","fvarp": [],"classOrPackagep": [],
{"type":"TASK","name":"put","addr":"(RJ)","loc":"d,44:12,44:15","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"put","fvarp": [],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"message","addr":"(MJ)","loc":"d,44:18,44:25","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"VAR","name":"message","addr":"(SJ)","loc":"d,44:18,44:25","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"REFDTYPE","name":"T","addr":"(NJ)","loc":"d,44:16,44:17","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}
{"type":"REFDTYPE","name":"T","addr":"(TJ)","loc":"d,44:16,44:17","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}
],"delayp": [],"valuep": [],"attrsp": []}
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{"type":"BEGIN","name":"","addr":"(YL)","loc":"d,87:25,87:30","generate":false,"genfor":false,"implied":false,"needProcess":false,"unnamed":true,"genforp": [],
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{"type":"BEGIN","name":"","addr":"(ON)","loc":"d,116:38,116:43","generate":false,"genfor":false,"implied":false,"needProcess":false,"unnamed":true,"genforp": [],
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]}
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{"type":"PARSEREF","name":"m_keyCount","addr":"(TN)","loc":"d,117:13,117:23","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],"timingControlp": []},
{"type":"RETURN","name":"","addr":"(ON)","loc":"d,118:13,118:19",
{"type":"RETURN","name":"","addr":"(UN)","loc":"d,118:13,118:19",
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{"type":"CONST","name":"?32?sh1","addr":"(VN)","loc":"d,118:20,118:21","dtypep":"(N)"}
]}
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{"type":"RETURN","name":"","addr":"(QN)","loc":"d,120:10,120:16",
{"type":"RETURN","name":"","addr":"(WN)","loc":"d,120:10,120:16",
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{"type":"CONST","name":"?32?sh0","addr":"(XN)","loc":"d,120:17,120:18","dtypep":"(N)"}
]}
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"stmtsp": [
{"type":"VAR","name":"s","addr":"(UP)","loc":"d,224:17,224:18","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"VAR","name":"s","addr":"(AQ)","loc":"d,224:17,224:18","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"string","addr":"(VP)","loc":"d,224:10,224:16","dtypep":"(VP)","keyword":"string","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"string","addr":"(BQ)","loc":"d,224:10,224:16","dtypep":"(BQ)","keyword":"string","generic":false,"rangep": []}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"STMTEXPR","name":"","addr":"(WP)","loc":"d,226:11,226:12",
{"type":"STMTEXPR","name":"","addr":"(CQ)","loc":"d,226:11,226:12",
"exprp": [
{"type":"DOT","name":"","addr":"(XP)","loc":"d,226:11,226:12","dtypep":"UNLINKED","colon":false,
{"type":"DOT","name":"","addr":"(DQ)","loc":"d,226:11,226:12","dtypep":"UNLINKED","colon":false,
"lhsp": [
{"type":"PARSEREF","name":"s","addr":"(YP)","loc":"d,226:10,226:11","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"s","addr":"(EQ)","loc":"d,226:10,226:11","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],
"rhsp": [
{"type":"TASKREF","name":"itoa","addr":"(ZP)","loc":"d,226:12,226:16","dtypep":"(FK)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],
{"type":"TASKREF","name":"itoa","addr":"(FQ)","loc":"d,226:12,226:16","dtypep":"(LK)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],
"pinsp": [
{"type":"ARG","name":"","addr":"(AQ)","loc":"d,226:17,226:24",
{"type":"ARG","name":"","addr":"(GQ)","loc":"d,226:17,226:24",
"exprp": [
{"type":"RAND","name":"","addr":"(BQ)","loc":"d,226:17,226:24","dtypep":"UNLINKED","seedp": []}
{"type":"RAND","name":"","addr":"(HQ)","loc":"d,226:17,226:24","dtypep":"UNLINKED","seedp": []}
]}
],"scopeNamep": []}
]}
]},
{"type":"STMTEXPR","name":"","addr":"(CQ)","loc":"d,227:10,227:23",
{"type":"STMTEXPR","name":"","addr":"(IQ)","loc":"d,227:10,227:23",
"exprp": [
{"type":"TASKREF","name":"set_randstate","addr":"(DQ)","loc":"d,227:10,227:23","dtypep":"(FK)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],
{"type":"TASKREF","name":"set_randstate","addr":"(JQ)","loc":"d,227:10,227:23","dtypep":"(LK)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],
"pinsp": [
{"type":"ARG","name":"","addr":"(EQ)","loc":"d,227:24,227:25",
{"type":"ARG","name":"","addr":"(KQ)","loc":"d,227:24,227:25",
"exprp": [
{"type":"PARSEREF","name":"s","addr":"(FQ)","loc":"d,227:24,227:25","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"s","addr":"(LQ)","loc":"d,227:24,227:25","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
]}
],"scopeNamep": []}
]},
{"type":"RETURN","name":"","addr":"(GQ)","loc":"d,228:10,228:16",
{"type":"RETURN","name":"","addr":"(MQ)","loc":"d,228:10,228:16",
"lhsp": [
{"type":"PARSEREF","name":"s","addr":"(HQ)","loc":"d,228:17,228:18","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"s","addr":"(NQ)","loc":"d,228:17,228:18","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
]}
],"scopeNamep": []},
{"type":"TASK","name":"set_randstate","addr":"(IQ)","loc":"d,231:21,231:34","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_randstate","fvarp": [],"classOrPackagep": [],
{"type":"TASK","name":"set_randstate","addr":"(OQ)","loc":"d,231:21,231:34","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_randstate","fvarp": [],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"s","addr":"(JQ)","loc":"d,231:42,231:43","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
{"type":"VAR","name":"s","addr":"(PQ)","loc":"d,231:42,231:43","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"string","addr":"(KQ)","loc":"d,231:35,231:41","dtypep":"(KQ)","keyword":"string","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"string","addr":"(QQ)","loc":"d,231:35,231:41","dtypep":"(QQ)","keyword":"string","generic":false,"rangep": []}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"STMTEXPR","name":"","addr":"(LQ)","loc":"d,232:10,232:18",
{"type":"STMTEXPR","name":"","addr":"(RQ)","loc":"d,232:10,232:18",
"exprp": [
{"type":"RAND","name":"","addr":"(MQ)","loc":"d,232:10,232:18","dtypep":"UNLINKED",
{"type":"RAND","name":"","addr":"(SQ)","loc":"d,232:10,232:18","dtypep":"UNLINKED",
"seedp": [
{"type":"DOT","name":"","addr":"(NQ)","loc":"d,232:20,232:21","dtypep":"UNLINKED","colon":false,
{"type":"DOT","name":"","addr":"(TQ)","loc":"d,232:20,232:21","dtypep":"UNLINKED","colon":false,
"lhsp": [
{"type":"PARSEREF","name":"s","addr":"(OQ)","loc":"d,232:19,232:20","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"s","addr":"(UQ)","loc":"d,232:19,232:20","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],
"rhsp": [
{"type":"FUNCREF","name":"atoi","addr":"(PQ)","loc":"d,232:21,232:25","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []}
{"type":"FUNCREF","name":"atoi","addr":"(VQ)","loc":"d,232:21,232:25","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []}
]}
]}
]}
],"scopeNamep": []}
],"extendsp": []},
{"type":"FUNC","name":"randomize","addr":"(QQ)","loc":"d,235:17,235:26","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"randomize",
{"type":"FUNC","name":"randomize","addr":"(WQ)","loc":"d,235:17,235:26","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"randomize",
"fvarp": [
{"type":"BASICDTYPE","name":"int","addr":"(RQ)","loc":"d,235:13,235:16","dtypep":"(RQ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(XQ)","loc":"d,235:13,235:16","dtypep":"(XQ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"ASSIGN","name":"","addr":"(SQ)","loc":"d,236:17,236:18","dtypep":"UNLINKED",
{"type":"ASSIGN","name":"","addr":"(YQ)","loc":"d,236:17,236:18","dtypep":"UNLINKED",
"rhsp": [
{"type":"CONST","name":"?32?sh0","addr":"(TQ)","loc":"d,236:19,236:20","dtypep":"(N)"}
{"type":"CONST","name":"?32?sh0","addr":"(ZQ)","loc":"d,236:19,236:20","dtypep":"(N)"}
],
"lhsp": [
{"type":"PARSEREF","name":"randomize","addr":"(UQ)","loc":"d,236:7,236:16","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
{"type":"PARSEREF","name":"randomize","addr":"(AR)","loc":"d,236:7,236:16","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
],"timingControlp": []}
],"scopeNamep": []}
]}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(FK)",
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(LK)",
"typesp": [
{"type":"BASICDTYPE","name":"integer","addr":"(XI)","loc":"d,34:27,34:28","dtypep":"(XI)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"integer","addr":"(DJ)","loc":"d,34:27,34:28","dtypep":"(DJ)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,36:32,36:33","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(WE)","loc":"d,53:22,53:24","dtypep":"(WE)","keyword":"logic","generic":true,"rangep": []},
{"type":"VOIDDTYPE","name":"","addr":"(FK)","loc":"d,54:21,54:30","dtypep":"(FK)","generic":false},
{"type":"VOIDDTYPE","name":"","addr":"(LK)","loc":"d,54:21,54:30","dtypep":"(LK)","generic":false},
{"type":"BASICDTYPE","name":"logic","addr":"(SD)","loc":"d,128:22,128:23","dtypep":"(SD)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(HO)","loc":"d,130:22,130:23","dtypep":"(HO)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(FP)","loc":"d,165:17,165:56","dtypep":"(FP)","keyword":"logic","range":"295:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(NO)","loc":"d,130:22,130:23","dtypep":"(NO)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(LP)","loc":"d,165:17,165:56","dtypep":"(LP)","keyword":"logic","range":"295:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"string","addr":"(DG)","loc":"d,165:10,165:16","dtypep":"(DG)","keyword":"string","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
@ -1082,9 +1100,9 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(VQ)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(BR)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(WQ)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(VQ)","varsp": [],"blocksp": [],"inlinesp": []}
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(CR)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BR)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

152
test_regress/t/t_sys_queue_unsup.out Normal file
View File

@ -0,0 +1,152 @@
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:22:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
22 | $q_initialize(1, 1, 3, status);
| ^~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:25:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
25 | $q_initialize(2, 2, 2, status);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:28:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
28 | $q_initialize(3, 0, 10, status);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:31:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
31 | $q_initialize(3, 3, 10, status);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:34:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
34 | $q_initialize(3, 1, 0, status);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:37:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
37 | $q_initialize(3, 1, -1, status);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:40:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize'
40 | $q_initialize(1, 2, 20, status);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:43:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
43 | $q_add(3, 0, 0, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:46:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
46 | $q_remove(3, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:49:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
49 | res = $q_full(3, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:52:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
52 | $q_exam(3, 1, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:55:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
55 | $q_add(2, 1, 1, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:58:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
58 | res = $q_full(2, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:62:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
62 | $q_add(2, 1, 2, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:65:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
65 | res = $q_full(2, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:69:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
69 | $q_exam(2, 1, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:72:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
72 | $q_exam(2, 3, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:75:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
75 | $q_exam(2, 5, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:79:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
79 | $q_add(2, 1, 3, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:82:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
82 | $q_remove(2, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:86:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
86 | res = $q_full(2, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:90:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
90 | $q_remove(2, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:95:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
95 | res = $q_full(2, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:99:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
99 | $q_exam(2, 1, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:102:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
102 | $q_exam(2, 3, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:105:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
105 | $q_exam(2, 4, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:109:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
109 | $q_remove(2, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:113:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
113 | $q_add(1, 2, 1, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:115:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
115 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:118:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
118 | $q_add(1, 2, 2, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:120:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
120 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:123:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
123 | $q_add(1, 2, 3, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:125:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
125 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:128:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
128 | $q_exam(1, 1, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:131:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
131 | $q_exam(1, 3, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:134:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
134 | $q_exam(1, 5, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:138:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
138 | $q_add(1, 2, 4, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:141:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
141 | $q_remove(1, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:146:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
146 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:150:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
150 | $q_remove(1, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:154:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
154 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:158:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add'
158 | $q_add(1, 2, 4, status);
| ^~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:160:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
160 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:164:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
164 | $q_remove(1, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:168:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
168 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:171:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove'
171 | $q_remove(1, job, value, status);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:175:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full'
175 | res = $q_full(1, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:178:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
178 | $q_exam(1, 1, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:181:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
181 | $q_exam(1, 3, value, status);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:184:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam'
184 | $q_exam(1, 4, value, status);
| ^~~~~~~
%Error: Exiting due to

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test_regress/t/t_sys_queue_unsup.py Executable file
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
test.passes()

195
test_regress/t/t_sys_queue_unsup.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
//
// Simple bi-directional alias test.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Based on iverilog/ivtest/ivltests/queue.v
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module top;
reg pass;
integer res, status, job, value;
initial begin
pass = 1'b1;
$q_initialize(1, 1, 3, status);
`checkd(status, 0);
$q_initialize(2, 2, 2, status);
`checkd(status, 0);
$q_initialize(3, 0, 10, status);
`checkd(status, 4);
$q_initialize(3, 3, 10, status);
`checkd(status, 4);
$q_initialize(3, 1, 0, status);
`checkd(status, 5);
$q_initialize(3, 1, -1, status);
`checkd(status, 5);
$q_initialize(1, 2, 20, status);
`checkd(status, 6);
$q_add(3, 0, 0, status);
`checkd(status, 2);
$q_remove(3, job, value, status);
`checkd(status, 2);
res = $q_full(3, status);
`checkd(status, 2);
$q_exam(3, 1, value, status);
`checkd(status, 2);
$q_add(2, 1, 1, status);
`checkd(status, 0);
res = $q_full(2, status);
`checkd(status, 0);
`checkd(res, 0);
$q_add(2, 1, 2, status);
`checkd(status, 0);
res = $q_full(2, status);
`checkd(status, 0);
`checkd(res, 1);
$q_exam(2, 1, value, status);
`checkd(status, 0);
`checkd(value, 2);
$q_exam(2, 3, value, status);
`checkd(status, 0);
`checkd(value, 2);
$q_exam(2, 5, value, status);
`checkd(status, 0);
`checkd(value, 0);
$q_add(2, 1, 3, status);
`checkd(status, 1);
$q_remove(2, job, value, status);
`checkd(status, 0);
`checkd(job, 1);
`checkd(value, 2);
res = $q_full(2, status);
`checkd(status, 0);
`checkd(res, 0);
$q_remove(2, job, value, status);
`checkd(status, 0);
`checkd(job, 1);
`checkd(value, 1);
res = $q_full(2, status);
`checkd(status, 0);
`checkd(res, 0);
$q_exam(2, 1, value, status);
`checkd(status, 0);
`checkd(value, 0);
$q_exam(2, 3, value, status);
`checkd(status, 0);
`checkd(value, 2);
$q_exam(2, 4, value, status);
`checkd(status, 0);
`checkd(value, 0);
$q_remove(2, job, value, status);
`checkd(status, 3);
$q_add(1, 2, 1, status);
`checkd(status, 0);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_add(1, 2, 2, status);
`checkd(status, 0);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_add(1, 2, 3, status);
`checkd(status, 0);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 1);
$q_exam(1, 1, value, status);
`checkd(status, 0);
`checkd(value, 3);
$q_exam(1, 3, value, status);
`checkd(status, 0);
`checkd(value, 3);
$q_exam(1, 5, value, status);
`checkd(status, 0);
`checkd(value, 0);
$q_add(1, 2, 4, status);
`checkd(status, 1);
$q_remove(1, job, value, status);
`checkd(status, 0);
`checkd(job, 2);
`checkd(value, 1);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_remove(1, job, value, status);
`checkd(status, 0);
`checkd(job, 2);
`checkd(value, 2);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_add(1, 2, 4, status);
`checkd(status, 0);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_remove(1, job, value, status);
`checkd(status, 0);
`checkd(job, 2);
`checkd(value, 3);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_remove(1, job, value, status);
`checkd(status, 0);
`checkd(job, 2);
`checkd(value, 4);
res = $q_full(1, status);
`checkd(status, 0);
`checkd(res, 0);
$q_exam(1, 1, value, status);
`checkd(status, 0);
`checkd(value, 0);
$q_exam(1, 3, value, status);
`checkd(status, 0);
`checkd(value, 3);
$q_exam(1, 4, value, status);
`checkd(status, 0);
`checkd(value, 0);
$q_remove(1, job, value, status);
`checkd(status, 3);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule