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@ -3923,6 +3923,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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<< (suggest.empty() ? "" : nodep->warnMore() + suggest)
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<< (suggest.empty() ? "" : nodep->warnMore() + suggest)
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<< '\n'
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<< '\n'
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<< nodep->warnContextPrimary() << decl);
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<< nodep->warnContextPrimary() << decl);
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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return;
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return;
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}
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}
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}
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}
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint()
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test.passes()
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@ -0,0 +1,16 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off PINNOTFOUND */
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module child ();
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endmodule
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module t;
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child u_child (
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.missing_port (1'b0)
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);
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endmodule
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