Commentary: Changes update

Changes

@@ -18,6 +18,7 @@ Verilator 5.051 devel
 * Add comments as a branch description in coverage .info files (#7843). [Eryk Szpotanski]
 * Add --enable-light-debug configure option (#7886). [Geza Lore, Testorrent USA, Inc.]
 * Add user-provided DPI-C function declarations (#7626) (#7893). [Jakub Michalski]
+* Add error on static virtual functions (#7932). [Igor Zaworski, Antmicro Ltd.]
 * Support a sequence used as an event control (#7797) (#7846). [Yilou Wang]
 * Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
 * Optimize more always blocks in DFG (#7775). [Geza Lore, Testorrent USA, Inc.]
@@ -25,18 +26,23 @@ Verilator 5.051 devel
 * Fix $display accepting streaming concat arguments (#7663) (#7890). [Jaeuk Lee]
 * Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
 * Fix unique0 case side effects (#7787). [Pawel Klopotek]
+* Fix mid-window disable iff (#7792) (#7869). [Yilou Wang]
 * Fix cleaning purity cache after assertions. [Geza Lore, Testorrent USA, Inc.]
 * Fix internal error for coverpoints that reference a covergroup formal parameter (#7853 partial) (#7889). [Matthew Ballance]
 * Fix clang++ ambiguous overload of '==' operator (#7863). [Pawel Kojma, Antmicro Ltd.]
 * Fix heap-use-after-free in `VlRNG::VlRNG()` (#7865). [Dragon-Git]
 * Fix mixed-width inside and dist range bounds failing randomization (#7875). [Yilou Wang]
+* Fix solve-before over array variables failing randomization (#7876). [Yilou Wang]
+* Fix scoped randomize with array members under rand_mode (#7877). [Yilou Wang]
 * Fix range delays with parameter bounds (#7882). [Artur Bieniek, Antmicro Ltd.]
 * Fix --coverage on labeled inline assert/cover property (#7898) (#7904). [Patrick Creighton]
 * Fix memory leak in VerilatedFst::close() (#7899). [Jakub Michalski]
+* Fix spurious FSM COVERIGN on comparisons (#7900) (#7908). [Yogish Sekhar]
 * Fix independent force of multiply instantiated signals (#7905). [Artur Bieniek, Antmicro Ltd.]
 * Fix release of forced port nets (#7907) (#7901). [Artur Bieniek, Antmicro Ltd.]
 * Fix VL_TO_STRING function for array of structs (#7912). [Kornel Uriasz, Antmicro Ltd.]
 * Fix queues falling into wrong template spec (#7914). [Adam Kostrzewski, Antmicro Ltd.]
+* Fix crash streaming an unpacked array of unpacked structs (#7917). [Nick Brereton]
 
 
 Verilator 5.050 2026-07-01

docs/guide/exe_sim.rst

@@ -114,7 +114,7 @@ Options:
    When a model was Verilated using :vlopt:`--x-initial unique
    <--x-initial>`, sets the simulation runtime initialization technique. 0
    = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See
-   :ref:`Unknown States`.
+   :ref:`Unknown States`.  Default is 0.
 
 .. option:: +verilator+seed+<value>
 

test_regress/t/t_class_static_virtual_method_bad.out

@@ -1,6 +1,6 @@
 %Error: t/t_class_static_virtual_method_bad.v:8:23: Static methods cannot be virtual
                                                   : ... note: In instance '$unit.Foo'
-    8 |   static virtual task foo(); endtask
+    8 |   static virtual task foo();
       |                       ^~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_static_virtual_method_bad.v

@@ -5,5 +5,6 @@
 // SPDX-License-Identifier: CC0-1.0
 
 class Foo;
-  static virtual task foo(); endtask
+  static virtual task foo();
+  endtask
 endclass

test_regress/t/t_cover_fsm_datapath_cmp.v

@@ -5,41 +5,46 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module datapath_only #(
-  parameter logic [15:0] MASK = 16'hff00,
-  parameter logic [15:0] MATCH = 16'h1200
+    parameter logic [15:0] MASK = 16'hff00,
+    parameter logic [15:0] MATCH = 16'h1200
 ) (
-  input logic [6:0] a,
-  input logic b,
-  input logic [15:0] data,
-  output logic concat_hit,
-  output logic masked_hit
+    input logic [6:0] a,
+    input logic b,
+    input logic [15:0] data,
+    output logic concat_hit,
+    output logic masked_hit
 );
   assign concat_hit = ({a, b} == 8'h00);
   assign masked_hit = (data & MASK) == MATCH;
 endmodule
 
 module t #(
-  parameter logic [15:0] MASK = 16'hff00,
-  parameter logic [15:0] MATCH = 16'h1200
+    parameter logic [15:0] MASK = 16'hff00,
+    parameter logic [15:0] MATCH = 16'h1200
 ) (
-  input logic clk,
-  input logic rst,
-  input logic go,
-  input logic [6:0] a,
-  input logic b,
-  input logic [15:0] data,
-  output logic busy,
-  output logic hit,
-  output logic concat_hit,
-  output logic masked_hit
+    input logic clk,
+    input logic rst,
+    input logic go,
+    input logic [6:0] a,
+    input logic b,
+    input logic [15:0] data,
+    output logic busy,
+    output logic hit,
+    output logic concat_hit,
+    output logic masked_hit
 );
-  typedef enum logic [1:0] { IDLE, RUN, DONE } state_t;
+  typedef enum logic [1:0] {
+    IDLE,
+    RUN,
+    DONE
+  } state_t;
   state_t state;
 
   always_ff @(posedge clk) begin
     if (rst) begin
       state <= IDLE;
-    end else begin
+    end
+    else begin
       case (state)
         IDLE: if (go) state <= RUN;
         RUN: state <= DONE;
@@ -53,10 +58,10 @@ module t #(
   assign hit = (data & MASK) == MATCH;
 
   datapath_only datapath_only_u (
-    .a(a),
-    .b(b),
-    .data(data),
-    .concat_hit(concat_hit),
-    .masked_hit(masked_hit)
+      .a(a),
+      .b(b),
+      .data(data),
+      .concat_hit(concat_hit),
+      .masked_hit(masked_hit)
   );
 endmodule

test_regress/t/t_property_disable_iff_counter.v

@@ -47,7 +47,8 @@ module t (
     if (phase == PERIOD - 1) begin
       phase <= 0;
       idx <= idx + 1;
-    end else begin
+    end
+    else begin
       phase <= phase + 1;
     end
     if (phase == 0) begin

test_regress/t/t_sched_hybrid_hazard.v

@@ -17,16 +17,16 @@ module t;
   // verilator lint_on UNOPTFLAT
 
   // verilator lint_off ALWCOMBORDER
-  always_comb xxx = cyc[0] ? ~yyy : xxx; // xxx will become hybrid sensitivity
-  always_comb yyy = cyc[0] ? ~xxx : yyy; // yyy will become hybrid sensitivity
+  always_comb xxx = cyc[0] ? ~yyy : xxx;  // xxx will become hybrid sensitivity
+  always_comb yyy = cyc[0] ? ~xxx : yyy;  // yyy will become hybrid sensitivity
   // verilator lint_on ALWCOMBORDER
 
   always @(posedge clk) begin
-     cyc <= cyc + 1;
-     if (cyc == 10) begin
-        $display("xxx^yyy=%x", xxx ^ yyy);
-        $write("*-* All Finished *-*\n");
-        $finish;
-     end
+    cyc <= cyc + 1;
+    if (cyc == 10) begin
+      $display("xxx^yyy=%x", xxx ^ yyy);
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
   end
 endmodule

test_regress/t/t_stream_unpacked_array_struct.v

@@ -13,11 +13,9 @@
 // source but then re-wrapped the now-packed expression in AstCvtArrayToPacked,
 // which EmitC dereferenced as an array.
 
-module t(  /*AUTOARG*/
-    // Inputs
-    clk
+module t(
+    input clk
 );
-  input clk;
 
   `define checkh(gotv, expv) \
     do if ((gotv) !== (expv)) begin \