Tests: Close some test coverage holes.

test_regress/driver.pl

@@ -1425,6 +1425,8 @@ sub _make_main {
     print $fh "    srand48(5);\n";  # Ensure determinism
     print $fh "    Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset};
     print $fh "    topp = new $VM_PREFIX(\"top\");\n";
+    print $fh "    Verilated::internalsDump()\n;" if $self->{verilated_debug};
+
     my $set;
     if ($self->sc) {
         print $fh "    topp->fastclk(fastclk);\n" if $self->{inputs}{fastclk};
@@ -1762,6 +1764,7 @@ sub files_identical {
                 # Don't put control chars into our source repository
                 $l1[$l] =~ s/\r/<#013>/mig;
                 $l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig;
+                $l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig;
                 if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) {
                     splice @l1, $l+1;  # Trunc rest
                     last;

test_regress/t/t_flag_version.pl

@@ -20,6 +20,22 @@ foreach my $prog (
     run(fails => 0,
         cmd => ["perl", $prog,
                 "--version"],
+        tee => $self->{verbose},
+        logfile => "$Self->{obj_dir}/t_help.log",
+        expect => qr/^Verilator/,
+        );
+
+    run(fails => 0,
+        cmd => ["perl", $prog,
+                "-V"],
+        tee => $self->{verbose},
+        logfile => "$Self->{obj_dir}/t_help.log",
+        expect => qr/^Verilator/,
+        );
+
+    run(fails => 0,
+        cmd => ["perl", $prog,
+                "-V"],
         logfile => "$Self->{obj_dir}/t_help.log",
         expect => qr/^Verilator/,
         );

test_regress/t/t_verilated_debug.out

@@ -1,5 +1,10 @@
 -V{t0,1}- Verilated::debug is on. Message prefix indicates {<thread>,<sequence_number>}.
 -V{t0,2}+    Vt_verilated_debug::_ctor_var_reset
+internalsDump:
+  Version: Verilator ###
+  Argv: obj_vlt/t_verilated_debug/Vt_verilated_debug
+  scopesDump:
+
 -V{t0,3}+++++TOP Evaluate Vt_verilated_debug::eval
 -V{t0,4}+    Vt_verilated_debug::_eval_debug_assertions
 -V{t0,5}+    Vt_verilated_debug::_eval_initial
@@ -15,6 +20,5 @@
 -V{t0,15}+    Vt_verilated_debug::_eval
 -V{t0,16}+    Vt_verilated_debug::_sequent__TOP__1
 *-* All Finished *-*
-- t/t_verilated_debug.v:16: Verilog $finish
 -V{t0,17}+    Vt_verilated_debug::_change_request
 -V{t0,18}+    Vt_verilated_debug::final

test_regress/t/t_verilated_debug.pl

@@ -20,7 +20,7 @@ execute(
     );
 
 if (!$Self->{vltmt}) {  # vltmt output may vary between thread exec order
-    files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename});
+    files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
 }
 
 ok(1);