Fixed signed number operation (#3294) (#3308)

docs/CONTRIBUTORS

@@ -84,6 +84,7 @@ Pieter Kapsenberg
 Piotr Binkowski
 Qingyao Sun
 Rafal Kapuscik
+Raynard Qiao
 Richard Myers
 Rupert Swarbrick
 Samuel Riedel

src/V3LinkDot.cpp

@@ -1092,6 +1092,10 @@ class LinkDotFindVisitor final : public VNVisitor {
                     } else {
                         findvarp->combineType(nodep);
                         findvarp->fileline()->modifyStateInherit(nodep->fileline());
+                        if (nodep->getChildDTypep()->numeric().isSigned() && 
+                        !findvarp->getChildDTypep()->numeric().isSigned()) {
+                            findvarp->getChildDTypep()->numeric(VSigning(true));
+                        }
                         AstBasicDType* const bdtypep
                             = VN_CAST(findvarp->childDTypep(), BasicDType);
                         if (bdtypep && bdtypep->implicit()) {

test_regress/t/t_math_signed_calc.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Raynard Qiao. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_signed_calc.v

@@ -0,0 +1,49 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This mode performs signed number computations in the case of a particular
+// interface definition.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Raynard Qiao.
+// SPDX-License-Identifier: CC0-1.0
+
+// issure 3294
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   reg [7:0] in0;
+   reg [7:0] in1;
+   reg [15:0] out;
+   initial begin
+      in0 = 'h2;
+      in1 = 'hff;
+   end
+   Test test(.in0, .in1, .out);
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out);
+`endif
+      if (out !== 'hfffe) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish; 
+   end
+
+endmodule
+
+
+module Test(in0, in1, out);
+  input [7:0] in0;
+  input [7:0] in1;
+  output  [15:0] out;
+  wire signed [7:0] in1;
+  wire signed [7:0] in0;
+  wire signed [15:0] out;
+
+  assign out = $signed({1'b0, in0}) * in1;      // this operator should be  signed multiplication
+endmodule
+
+