Commentary: Changes update

Changes

@@ -16,12 +16,27 @@ Verilator 5.051 devel
 **Other:**
 
 * Add comments as a branch description in coverage .info files (#7843). [Eryk Szpotanski]
+* Add --enable-light-debug configure option (#7886). [Geza Lore, Testorrent USA, Inc.]
+* Add user-provided DPI-C function declarations (#7626) (#7893). [Jakub Michalski]
+* Support a sequence used as an event control (#7797) (#7846). [Yilou Wang]
 * Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
+* Optimize more always blocks in DFG (#7775). [Geza Lore, Testorrent USA, Inc.]
+* Optimize assertion NFAs using bit-vector ring buffers (#7885). [Artur Bieniek, Antmicro Ltd.]
+* Fix $display accepting streaming concat arguments (#7663) (#7890). [Jaeuk Lee]
 * Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
 * Fix unique0 case side effects (#7787). [Pawel Klopotek]
 * Fix cleaning purity cache after assertions. [Geza Lore, Testorrent USA, Inc.]
+* Fix internal error for coverpoints that reference a covergroup formal parameter (#7853 partial) (#7889). [Matthew Ballance]
 * Fix clang++ ambiguous overload of '==' operator (#7863). [Pawel Kojma, Antmicro Ltd.]
 * Fix heap-use-after-free in `VlRNG::VlRNG()` (#7865). [Dragon-Git]
+* Fix mixed-width inside and dist range bounds failing randomization (#7875). [Yilou Wang]
+* Fix range delays with parameter bounds (#7882). [Artur Bieniek, Antmicro Ltd.]
+* Fix --coverage on labeled inline assert/cover property (#7898) (#7904). [Patrick Creighton]
+* Fix memory leak in VerilatedFst::close() (#7899). [Jakub Michalski]
+* Fix independent force of multiply instantiated signals (#7905). [Artur Bieniek, Antmicro Ltd.]
+* Fix release of forced port nets (#7907) (#7901). [Artur Bieniek, Antmicro Ltd.]
+* Fix VL_TO_STRING function for array of structs (#7912). [Kornel Uriasz, Antmicro Ltd.]
+* Fix queues falling into wrong template spec (#7914). [Adam Kostrzewski, Antmicro Ltd.]
 
 
 Verilator 5.050 2026-07-01

test_regress/t/t_assert_inline_coverage.v

@@ -22,15 +22,18 @@ module t (
     if (!rst_n) begin
       q <= 1'b0;
       cnt <= '0;
-    end else if (en) begin
+    end
+    else if (en) begin
       q <= ~q;
       cnt <= cnt + 8'd1;
     end
   end
 
-  a : assert property (@(posedge clk) !rst_n |=> q == 1'b0);
+  a :
+  assert property (@(posedge clk) !rst_n |=> q == 1'b0);
 
-  c : cover property (@(posedge clk) disable iff (!rst_n) en && cnt == $past(cnt));
+  c :
+  cover property (@(posedge clk) disable iff (!rst_n) en && cnt == $past(cnt));
 
   always @(posedge clk) begin
     cyc <= cyc + 1;

test_regress/t/t_dpi_decl.v

@@ -4,12 +4,18 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
-  import "DPI-C" function string func(input string arg) /*verilator dpi_c_decl "char* func(const char*)"*/;
+  import "DPI-C" function string func(
-  import "DPI-C" function string func_with_specifier(input string arg) /*verilator dpi_c_decl "char* func_with_specifier(const char*) throw()"*/;
+    input string arg
+  )  /*verilator dpi_c_decl "char* func(const char*)"*/;
+  import "DPI-C" function string func_with_specifier(
+    input string arg
+  )  /*verilator dpi_c_decl "char* func_with_specifier(const char*) throw()"*/;
 
   initial begin
     `checks(func("arg"), "abc");

test_regress/t/t_dpi_decl_bad.out

@@ -1,4 +1,4 @@
-%Error-BADVLTPRAGMA: t/t_dpi_decl_bad.v:8:57: No function declaration provided in /*verilator dpi_c_decl*/ meta-comment
+%Error-BADVLTPRAGMA: t/t_dpi_decl_bad.v:8:58: No function declaration provided in /*verilator dpi_c_decl*/ meta-comment
     8 |   import "DPI-C" function string func(input string arg)  /*verilator dpi_c_decl*/;
       |                                                          ^~~~~~~~~~~~~~~~~~~~~~~~
                      ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest

test_regress/t/t_force_immediate_release_port_net.v

@@ -16,12 +16,12 @@ module t;
   wire [7:0] f;
   wire [31:0] g;
   logic [4:0] idx = 0;
-  sub s(b);
+  sub s (b);
-  sub8 s_sel(d[7:0]);
+  sub8 s_sel (d[7:0]);
-  sub8 s_const(8'h7c);
+  sub8 s_const (8'h7c);
-  subout s_out(e[idx+:8]);
+  subout s_out (e[idx+:8]);
-  subout s_out_simple(f);
+  subout s_out_simple (f);
-  subout s_out_slice(g[15:8]);
+  subout s_out_slice (g[15:8]);
 
   initial begin
     #1;
@@ -76,12 +76,18 @@ module t;
 
 endmodule
 
-module sub(input logic [31:0] c);
+module sub (
+    input logic [31:0] c
+);
 endmodule
 
-module sub8(input logic [7:0] c);
+module sub8 (
+    input logic [7:0] c
+);
 endmodule
 
-module subout(output logic [7:0] c);
+module subout (
+    output logic [7:0] c
+);
   assign c = 8'h5a;
 endmodule

test_regress/t/t_force_scope.v

@@ -4,13 +4,15 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-module child(input wire i);
+module child (
+    input wire i
+);
   /*verilator no_inline_module*/
 endmodule
 
 module t;
-   child a(.i(1'b0));
+  child a (.i(1'b0));
-   child b(.i(1'b0));
+  child b (.i(1'b0));
 
   initial begin
     force a.i = 1'b1;

test_regress/t/t_force_scope_assign.v

@@ -4,7 +4,10 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-module child(input wire drive, output wire observed);
+module child (
+    input wire drive,
+    output wire observed
+);
   /*verilator no_inline_module*/
 
   logic value;
@@ -22,8 +25,14 @@ module t;
   wire b_observed;
   bit done;
 
-  child a(.drive(1'b1), .observed(a_observed));
+  child a (
-  child b(.drive(1'b0), .observed(b_observed));
+      .drive(1'b1),
+      .observed(a_observed)
+  );
+  child b (
+      .drive(1'b0),
+      .observed(b_observed)
+  );
 
   always @(a_observed or b_observed) begin
     if (!done && a_observed === 1'b1) begin

test_regress/t/t_property_delay_large.v

@@ -45,7 +45,8 @@ module t (
   assert property (@(posedge clk) fixed_a |-> ##1024 fixed_b)
   else fixed_fail_q.push_back($sampled(cyc) + 1);
 
-  cover property (@(posedge clk) range_a ##[5:300] range_b) range_pass_q.push_back($sampled(cyc) + 1);
+  cover property (@(posedge clk) range_a ##[5:300] range_b)
+    range_pass_q.push_back($sampled(cyc) + 1);
 
   assert property (@(posedge clk) range_a |-> ##[5:300] range_b)
   else range_fail_q.push_back($sampled(cyc) + 1);