Fix mis-optimized identical submodule subtract, bug581.
This commit is contained in:
Wilson Snyder
parent
38b9fa7b93
commit
30f6c0e105
2
Changes
2
Changes
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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Add +1364-1995ext and similar language options, bug532. [Jeremy Bennett]
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**** Fix mis-optimized identical submodule subtract, bug581. [Charlie Brej]
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**** Fix compile issues on MSVCC, bug571, bug577. [Amir Gonnen]
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**** Fix --debug overriding preceding --dump-treei, bug580. [Jeremy Bennett]
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@ -416,6 +416,7 @@ private:
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// If cleanup sameTree to be smarter, this can be restored.
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//return node1p->sameTree(node2p);
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return node1p->castVarRef()->varp() == node2p->castVarRef()->varp()
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&& node1p->castVarRef()->varScopep() == node2p->castVarRef()->varScopep()
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&& node1p->castVarRef()->lvalue() == node2p->castVarRef()->lvalue();
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} else {
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return false;
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@ -20,6 +20,7 @@ use vars qw ($Debug %Vars $Driver $Fork);
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use POSIX qw(strftime);
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$::Driver = 1;
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$::Have_Forker = 0;
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eval "use Parallel::Forker; \$Fork=Parallel::Forker->new(use_sig_child=>1); \$::Have_Forker=1;";
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$Fork = Forker->new(use_sig_child=>1) if !$Fork;
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@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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@ -0,0 +1,280 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [7:0] operand_a = crc[7:0];
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wire [7:0] operand_b = crc[15:8];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [6:0] out; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[6:0]),
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// Inputs
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.clk (clk),
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.operand_a (operand_a[7:0]),
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.operand_b (operand_b[7:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {57'h0, out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hf15989544a22e48a
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test
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(
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// Inputs
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input wire clk,
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input wire [7:0] operand_a, // operand a
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input wire [7:0] operand_b, // operand b
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// Outputs
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output wire [6:0] out
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);
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wire [6:0] clz_a;
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wire [6:0] clz_b;
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clz u_clz_a
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(
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// Inputs
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.data_i (operand_a),
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.out (clz_a));
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clz u_clz_b
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(
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// Inputs
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.data_i (operand_b),
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.out (clz_b));
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assign out = clz_a - clz_b;
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`ifdef TEST_VERBOSE
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always @(posedge clk)
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$display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
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`endif
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endmodule
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`define def_0000_001x 8'b0000_0010, 8'b0000_0011
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`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111
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`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011
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`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111
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`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx
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`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011
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`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111
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`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011
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`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111
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`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011
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`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111
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`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011
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`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111
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`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011
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`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111
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`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011
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`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111
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`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011
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`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111
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`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011
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`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111
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`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011
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`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111
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`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011
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`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111
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`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011
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`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111
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`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011
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`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111
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`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011
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`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111
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`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011
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`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111
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`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011
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`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111
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`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011
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`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111
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`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011
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`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111
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`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011
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`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111
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`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011
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`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111
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`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011
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`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111
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`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011
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`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111
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`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011
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`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111
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`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011
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`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111
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`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011
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`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111
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`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011
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`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111
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`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011
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`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111
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`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011
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`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111
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`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011
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`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111
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`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011
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`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111
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`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011
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`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111
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`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx
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`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx
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`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx
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`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx
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`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx
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`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx
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`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx
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`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx
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`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx
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`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx
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`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx
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`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx
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`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx
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`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx
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`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx
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`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \
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`def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx
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`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx
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`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx
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module clz(
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input wire [7:0] data_i,
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output wire [6:0] out
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);
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// -----------------------------
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// Reg declarations
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// -----------------------------
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reg [2:0] clz_byte0;
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reg [2:0] clz_byte1;
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reg [2:0] clz_byte2;
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reg [2:0] clz_byte3;
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assign out = data_i[6:0];
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always @*
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case (data_i)
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`def_1xxx_xxxx : clz_byte0 = 3'b000;
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`def_01xx_xxxx : clz_byte0 = 3'b001;
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`def_001x_xxxx : clz_byte0 = 3'b010;
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`def_0001_xxxx : clz_byte0 = 3'b011;
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`def_0000_1xxx : clz_byte0 = 3'b100;
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`def_0000_01xx : clz_byte0 = 3'b101;
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`def_0000_001x : clz_byte0 = 3'b110;
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8'b0000_0001 : clz_byte0 = 3'b111;
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8'b0000_0000 : clz_byte0 = 3'b111;
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default : clz_byte0 = 3'bxxx;
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endcase
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always @*
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case (data_i)
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`def_1xxx_xxxx : clz_byte1 = 3'b000;
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`def_01xx_xxxx : clz_byte1 = 3'b001;
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`def_001x_xxxx : clz_byte1 = 3'b010;
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`def_0001_xxxx : clz_byte1 = 3'b011;
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`def_0000_1xxx : clz_byte1 = 3'b100;
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`def_0000_01xx : clz_byte1 = 3'b101;
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`def_0000_001x : clz_byte1 = 3'b110;
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8'b0000_0001 : clz_byte1 = 3'b111;
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8'b0000_0000 : clz_byte1 = 3'b111;
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default : clz_byte1 = 3'bxxx;
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endcase
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always @*
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case (data_i)
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`def_1xxx_xxxx : clz_byte2 = 3'b000;
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`def_01xx_xxxx : clz_byte2 = 3'b001;
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`def_001x_xxxx : clz_byte2 = 3'b010;
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`def_0001_xxxx : clz_byte2 = 3'b011;
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`def_0000_1xxx : clz_byte2 = 3'b100;
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`def_0000_01xx : clz_byte2 = 3'b101;
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`def_0000_001x : clz_byte2 = 3'b110;
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8'b0000_0001 : clz_byte2 = 3'b111;
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8'b0000_0000 : clz_byte2 = 3'b111;
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default : clz_byte2 = 3'bxxx;
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endcase
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always @*
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case (data_i)
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`def_1xxx_xxxx : clz_byte3 = 3'b000;
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`def_01xx_xxxx : clz_byte3 = 3'b001;
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`def_001x_xxxx : clz_byte3 = 3'b010;
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`def_0001_xxxx : clz_byte3 = 3'b011;
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`def_0000_1xxx : clz_byte3 = 3'b100;
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`def_0000_01xx : clz_byte3 = 3'b101;
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`def_0000_001x : clz_byte3 = 3'b110;
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8'b0000_0001 : clz_byte3 = 3'b111;
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8'b0000_0000 : clz_byte3 = 3'b111;
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default : clz_byte3 = 3'bxxx;
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endcase
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endmodule // clz
|
||||
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Reference in New Issue