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Cleanup missing copyrights and those on simply copied files. No functional change.

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This commit is contained in:
Wilson Snyder
2023-01-20 20:42:30 -05:00
parent 79f99dddf7
commit 30d6edd2e5
116 changed files with 274 additions and 161 deletions
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docs/guide/conf.py
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@@ -1,6 +1,7 @@
# pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
#
# Configuration file for Verilator's Sphinx documentation builder.
# Copyright 2003-2023 by Wilson Snyder.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
#
# This file only contains overridden options. For a full list:
docs/internals.rst
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@@ -1876,4 +1876,6 @@ Copyright 2008-2023 by Wilson Snyder. Verilator is free software; you can
redistribute it and/or modify it under the terms of either the GNU Lesser
General Public License Version 3 or the Perl Artistic License Version 2.0.
SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
docs/verilated.dox
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@@ -1,4 +1,4 @@
PROJECT_NAME = "Verilog to Routing - ABC"
PROJECT_NAME = "Verilator"
INPUT = ../../include
OUTPUT_DIRECTORY = _build/doxygen/verilated
docs/xml.rst
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@@ -74,4 +74,6 @@ Copyright 2020-2023 by Wilson Snyder. Verilator is free software; you can
redistribute it and/or modify it under the terms of either the GNU Lesser
General Public License Version 3 or the Perl Artistic License Version 2.0.
SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png