Merge 4f8c094f6e into ff37860e0c
This commit is contained in:
Nick Brereton
GitHub
commit
30b4dd6884
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@ -34,6 +34,9 @@ public:
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std::vector<AstNodeStmt*> m_inits; // Initialization statements for previous values
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std::vector<AstNodeStmt*> m_preUpdates; // Pre update assignments
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std::vector<AstNodeStmt*> m_postUpdates; // Post update assignments
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// Destructive post updates (for example event clearFired) that may need
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// to run once before entering a fresh dynamic wait loop.
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std::vector<AstNodeStmt*> m_destructivePostUpdates;
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std::vector<AstVar*> m_vars; // Created temporary variables
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};
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@ -278,8 +281,10 @@ private:
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AstCMethodHard* const clearp
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= new AstCMethodHard{flp, currp(), VCMethod::EVENT_CLEAR_FIRED};
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clearp->dtypeSetVoid();
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m_results.m_postUpdates.push_back(
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wrapStmtWithNullCheck(flp, clearp->makeStmt(), baseClassRefp));
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AstNodeStmt* const clearStmtp
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= wrapStmtWithNullCheck(flp, clearp->makeStmt(), baseClassRefp);
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m_results.m_postUpdates.push_back(clearStmtp);
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m_results.m_destructivePostUpdates.push_back(clearStmtp->cloneTree(false));
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// Get 'fired' state
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AstCMethodHard* const callp
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@ -625,15 +625,6 @@ class TimingControlVisitor final : public VNVisitor {
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return !nodep->isPure();
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});
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}
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// Returns true if the given trigger expression needs a destructive post update after trigger
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// evaluation. Currently this only applies to named events.
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bool destructivePostUpdate(AstNode* const exprp) const {
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return exprp->exists([](const AstNode* const nodep) {
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const AstNodeDType* const dtypep = nodep->dtypep();
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const AstBasicDType* const basicp = dtypep ? dtypep->skipRefp()->basicp() : nullptr;
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return basicp && basicp->isEvent();
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});
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}
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// Creates a trigger scheduler variable
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AstVarScope* getCreateTriggerSchedulerp(AstSenTree* const sentreep) {
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if (!sentreep->user1p()) {
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@ -1065,7 +1056,6 @@ class TimingControlVisitor final : public VNVisitor {
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= createTemp(flp, m_dynTrigNames.get(nodep), nodep->findBitDType(), nodep);
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auto* const initp = new AstAssign{flp, new AstVarRef{flp, trigvscp, VAccess::WRITE},
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new AstConst{flp, AstConst::BitFalse{}}};
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nodep->addHereThisAsNext(initp);
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// Await the eval step with the dynamic trigger scheduler. First, create the method
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// call
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auto* const evalMethodp = new AstCMethodHard{
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@ -1085,10 +1075,10 @@ class TimingControlVisitor final : public VNVisitor {
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// Get the SenExprBuilder results
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const SenExprBuilder::Results senResults = m_senExprBuilderp->getAndClearResults();
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localizeVars(m_procp, senResults.m_vars);
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// Put all and inits before the trigger eval loop
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for (AstNodeStmt* const stmtp : senResults.m_inits) {
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nodep->addHereThisAsNext(stmtp);
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}
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// If post updates are destructive (e.g. clearFired on events), perform a
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// conservative pre-clear once before entering the wait loop so stale state from a
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// previous wait does not cause an immediate false-positive trigger.
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const bool hasDestructivePostUpdates = !senResults.m_destructivePostUpdates.empty();
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// Create the trigger eval loop, which will await the evaluation step and check the
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// trigger
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AstNodeExpr* const condp
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@ -1109,7 +1099,7 @@ class TimingControlVisitor final : public VNVisitor {
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loopp->addStmtsp(anyTriggeredMethodp->makeStmt());
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// If the post update is destructive (e.g. event vars are cleared), create an await for
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// the post update step
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if (destructivePostUpdate(sentreep)) {
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if (hasDestructivePostUpdates) {
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AstCAwait* const awaitPostUpdatep = awaitEvalp->cloneTree(false);
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VN_AS(awaitPostUpdatep->exprp(), CMethodHard)->method(VCMethod::SCHED_POST_UPDATE);
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loopp->addStmtsp(awaitPostUpdatep);
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@ -1120,8 +1110,20 @@ class TimingControlVisitor final : public VNVisitor {
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AstCAwait* const awaitResumep = awaitEvalp->cloneTree(false);
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VN_AS(awaitResumep->exprp(), CMethodHard)->method(VCMethod::SCHED_RESUMPTION);
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AstNode::addNext<AstNodeStmt, AstNodeStmt>(loopp, awaitResumep);
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// Replace the event control with the loop
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nodep->replaceWith(loopp);
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// Replace the event control with one explicit stmt chain:
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// init -> [inits] -> [optional destructive pre-clears] -> loop -> awaitResumption
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AstNodeStmt* chainp = nullptr;
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chainp = AstNode::addNextNull(chainp, initp);
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for (AstNodeStmt* const stmtp : senResults.m_inits) {
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chainp = AstNode::addNextNull(chainp, stmtp);
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}
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if (hasDestructivePostUpdates) {
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for (AstNodeStmt* const stmtp : senResults.m_destructivePostUpdates) {
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chainp = AstNode::addNextNull(chainp, stmtp);
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}
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}
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chainp = AstNode::addNextNull(chainp, loopp);
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nodep->replaceWith(chainp);
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} else {
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auto* const sentreep = m_finder.getSenTree(nodep->sentreep());
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nodep->sentreep()->unlinkFrBack()->deleteTree();
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary", "--timing", "--vpi", "--bbox-sys"])
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test.execute(fails=True)
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test.passes()
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@ -0,0 +1,180 @@
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// DESCRIPTION: Verilator: APB clocking readback regression
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`timescale 1ns/1ns
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface apb_if(input bit pclk);
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wire [31:0] paddr;
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wire psel;
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wire penable;
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wire pwrite;
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wire [31:0] prdata;
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wire [31:0] pwdata;
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clocking mck @(posedge pclk);
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output paddr, psel, penable, pwrite, pwdata;
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input prdata;
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endclocking
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clocking pck @(posedge pclk);
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input paddr, psel, penable, pwrite, prdata, pwdata;
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endclocking
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endinterface
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module blk(apb_if apb, input bit rst);
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logic [31:0] mode;
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logic [31:0] rate;
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logic [31:0] pr_data;
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assign apb.prdata = (apb.psel && apb.penable) ? pr_data : 'z;
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always_comb begin
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pr_data = 32'h0;
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case (apb.paddr[7:0])
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8'h00: pr_data = mode;
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8'h04: pr_data = rate;
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default: ;
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endcase
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end
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always_ff @(posedge apb.pclk) begin
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if (rst) begin
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mode <= 0;
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rate <= 0;
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end else if (apb.psel && apb.penable && apb.pwrite) begin
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case (apb.paddr[7:0])
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8'h00: mode <= apb.pwdata;
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8'h04: rate <= apb.pwdata;
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default: ;
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endcase
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end
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end
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endmodule
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module soc(apb_if apb, input bit rst);
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apb_if apb0(apb.pclk);
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apb_if apb1(apb.pclk);
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apb_if apb2(apb.pclk);
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blk blk0(apb0, rst);
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blk blk1(apb1, rst);
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blk blk2(apb2, rst);
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assign apb0.paddr = apb.paddr;
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assign apb0.psel = ((apb.paddr[31:8] == 24'h000000) || (apb.paddr[31:8] == 24'h030000));
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assign apb0.penable = apb.penable;
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assign apb0.pwrite = apb.pwrite;
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assign apb0.pwdata = apb.pwdata;
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assign apb.prdata = apb0.prdata;
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assign apb1.paddr = apb.paddr;
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assign apb1.psel = ((apb.paddr[31:8] == 24'h010000) || (apb.paddr[31:8] == 24'h030000));
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assign apb1.penable = apb.penable;
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assign apb1.pwrite = apb.pwrite;
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assign apb1.pwdata = apb.pwdata;
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assign apb.prdata = apb1.prdata;
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assign apb2.paddr = apb.paddr;
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assign apb2.psel = ((apb.paddr[31:8] == 24'h020000) || (apb.paddr[31:8] == 24'h030000));
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assign apb2.penable = apb.penable;
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assign apb2.pwrite = apb.pwrite;
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assign apb2.pwdata = apb.pwdata;
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assign apb.prdata = apb2.prdata;
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endmodule
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class Master;
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virtual apb_if vif;
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function new(virtual apb_if vif);
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this.vif = vif;
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endfunction
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task read(input logic [31:0] addr, output logic [31:0] data_mck);
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vif.mck.paddr <= addr;
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vif.mck.pwrite <= 1'b0;
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vif.mck.psel <= 1'b1;
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@(vif.mck);
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vif.mck.penable <= 1'b1;
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@(vif.mck);
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data_mck = vif.mck.prdata;
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$display("READ_SAMPLE t=%0t addr=%08x mck=%08x", $time, addr, data_mck);
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vif.mck.psel <= 1'b0;
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vif.mck.penable <= 1'b0;
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endtask
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task write(input logic [31:0] addr, input logic [31:0] data);
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vif.mck.paddr <= addr;
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vif.mck.pwdata <= data;
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vif.mck.pwrite <= 1'b1;
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vif.mck.psel <= 1'b1;
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@(vif.mck);
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vif.mck.penable <= 1'b1;
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@(vif.mck);
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$display("WRITE_SAMPLE t=%0t addr=%08x data=%08x", $time, addr, data);
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vif.mck.psel <= 1'b0;
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vif.mck.penable <= 1'b0;
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endtask
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endclass
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module t;
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bit clk = 0;
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bit rst = 1;
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apb_if apb(clk);
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soc dut(apb, rst);
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Master m;
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always #10 clk = ~clk;
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initial begin
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logic [31:0] d0, d1, d2;
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logic [31:0] m0, m1, m2;
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m = new(apb);
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repeat (2) @(posedge clk);
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rst = 0;
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// First phase: direct mode initialization then three reads.
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// This catches first-read timing regressions.
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dut.blk0.mode = 32'h5;
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dut.blk1.mode = 32'h5;
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dut.blk2.mode = 32'h5;
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@(posedge clk);
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m.read(32'h0000_0000, d0);
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m.read(32'h0100_0000, d1);
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m.read(32'h0200_0000, d2);
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$display("FIRST_RESULT d0=%08x d1=%08x d2=%08x", d0, d1, d2);
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`checkd(d0, 32'h0000_0005);
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`checkd(d1, 32'h0000_0005);
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`checkd(d2, 32'h0000_0005);
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// Second phase: broadcast write through the clocking path and readback.
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// This catches mck.prdata sampling regressions.
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m.write(32'h0300_0000, 32'h5);
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m.read(32'h0000_0000, m0);
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m.read(32'h0100_0000, m1);
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m.read(32'h0200_0000, m2);
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$display("SECOND_RESULT m0=%08x m1=%08x m2=%08x", m0, m1, m2);
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`checkd(m0, 32'h0000_0005);
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`checkd(m1, 32'h0000_0005);
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`checkd(m2, 32'h0000_0005);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(apb.pck) begin
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if (apb.pck.psel && apb.pck.penable && !apb.pck.pwrite) begin
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$display("MON_READ t=%0t addr=%08x data=%08x", $time, apb.pck.paddr, apb.pck.prdata);
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end
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end
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endmodule
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