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https://github.com/verilator/verilator.git
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Internals: Fix many clang-tidy issues. No functional change intended.
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+6
-4
@@ -577,7 +577,9 @@ const char* AstScope::broken() const {
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void AstScope::cloneRelink() {
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if (m_aboveScopep && m_aboveScopep->clonep()) m_aboveScopep->clonep();
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if (m_aboveCellp && m_aboveCellp->clonep()) m_aboveCellp->clonep();
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if (m_modp && ((AstNode*)m_modp)->clonep()) ((AstNode*)m_modp)->clonep();
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if (m_modp && static_cast<AstNode*>(m_modp)->clonep()) {
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static_cast<AstNode*>(m_modp)->clonep();
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}
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}
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string AstScope::nameDotless() const {
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@@ -651,7 +653,7 @@ bool AstSenTree::hasCombo() const {
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void AstTypeTable::clearCache() {
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// When we mass-change widthMin in V3WidthCommit, we need to correct the table.
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// Just clear out the maps; the search functions will be used to rebuild the map
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for (int i=0; i<(int)(AstBasicDTypeKwd::_ENUM_MAX); ++i) {
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for (int i=0; i < static_cast<int>(AstBasicDTypeKwd::_ENUM_MAX); ++i) {
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m_basicps[i] = NULL;
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}
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for (int isbit=0; isbit<_IDX0_MAX; ++isbit) {
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@@ -701,7 +703,7 @@ AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kw
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else if (kwd == AstBasicDTypeKwd::BIT) idx = IDX0_BIT;
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else fl->v3fatalSrc("Bad kwd for findLogicBitDType");
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std::pair<int,int> widths = make_pair(width,widthMin);
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LogicMap& mapr = m_logicMap[idx][(int)numeric];
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LogicMap& mapr = m_logicMap[idx][static_cast<int>(numeric)];
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LogicMap::const_iterator it = mapr.find(widths);
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if (it != mapr.end()) return it->second;
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//
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@@ -991,7 +993,7 @@ void AstMTaskBody::dump(std::ostream& str) {
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}
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void AstTypeTable::dump(std::ostream& str) {
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this->AstNode::dump(str);
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for (int i=0; i<(int)(AstBasicDTypeKwd::_ENUM_MAX); ++i) {
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for (int i=0; i < static_cast<int>(AstBasicDTypeKwd::_ENUM_MAX); ++i) {
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if (AstBasicDType* subnodep=m_basicps[i]) {
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str<<endl; // Newline from caller, so newline first
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str<<"\t\t"<<std::setw(8)<<AstBasicDTypeKwd(i).ascii();
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