fix concatenation + type casting bug

src/V3Width.cpp

@@ -2112,6 +2112,7 @@ class WidthVisitor final : public VNVisitor {
                                               VFlagChildDType{}, refp};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
+            userIterate(newp, m_vup);
         } else {
             nodep->v3warn(E_UNSUPPORTED,
                           "Unsupported: Cast to " << nodep->dtp()->prettyTypeName());
@@ -2126,6 +2127,12 @@ class WidthVisitor final : public VNVisitor {
         if (m_vup->prelim()) {
             if (debug() >= 9) nodep->dumpTree("-  CastPre: ");
             // if (debug()) nodep->backp()->dumpTree("-  CastPreUpUp: ");
+            if (VN_IS(nodep->fromp(), Signed)) {
+                AstSigned* fromp = VN_AS(nodep->fromp(), Signed);
+                AstNode* lhsp = fromp->lhsp()->unlinkFrBack();
+                fromp->replaceWith(lhsp);
+                VL_DO_DANGLING(fromp->deleteTree(), fromp);
+            }
             userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
             if (debug() >= 9) nodep->dumpTree("-  CastDit: ");
             AstNodeDType* const toDtp = nodep->dtypep()->skipRefToEnump();
@@ -7334,6 +7341,7 @@ class WidthVisitor final : public VNVisitor {
         // Returns the new underp
         // Conversion to/from doubles and integers are before iterating.
         UASSERT_OBJ(stage == FINAL, nodep, "Bad state to iterateCheck");
+        if (underp) { UINFO(1, "underp dtype = " << underp->dtypep() << endl); }
         UASSERT_OBJ(underp && underp->dtypep(), nodep,
                     "Node has no type");  // Perhaps forgot to do a prelim visit on it?
         if (VN_IS(underp, NodeDType)) {  // Note the node itself, not node's data type

test_regress/t/t_concatenate_casts.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("simulator")
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_concatenate_casts.v

@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+
+module t;
+
+    typedef logic [7:0] foo_t;
+    typedef logic [31:0] bar_t;
+
+    bar_t [1:0] the_bars;
+
+    foo_t [0:0][1:0] the_foos;
+
+    always_comb begin
+        the_bars = {32'd7, 32'd8};
+        the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])};
+        // NOCOMMIT
+        // the_foos[0][1] = foo_t'(the_bars[1]);
+        // the_foos[0][0] = foo_t'(the_bars[0]);
+    end
+
+    initial begin
+        // NOCOMMIT -- displays
+        $display($bits(the_foos));
+        $display($bits(the_foos[0]));
+        $display($bits(the_foos[0][0]));
+        $display(the_foos[0][1]);
+        $display("===> %x", the_foos);
+        if (the_foos != 'h0708) $stop();
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+endmodule