Tests: Add t_math_msvc_64, from bug214

test_regress/t/t_math_msvc_64.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 verilator_flags2 => ["--compiler msvc"],  # Bug requires msvc
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_math_msvc_64.v

@@ -0,0 +1,74 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   
+   reg [89:0]	in;   
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [89:0] 		out;			// From test of Test.v
+   wire [44:0] 		line0;
+   wire [44:0] 		line1;
+   // End of automatics
+   
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[89:0]),
+	      .line0			(line0[44:0]),
+	      .line1			(line1[44:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[89:0]));
+  
+   // Test loop
+   always @ (posedge clk) begin   
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
+`endif
+      cyc <= cyc + 1;      
+      if (cyc==0) begin
+	 // Setup	 
+	 in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
+      end
+      else if (cyc==10) begin
+         if (in==out) begin
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+	 else begin
+	   $write("*-* Failed!! *-*\n");
+	    $finish;
+	 end
+      end      
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   line0, line1, out,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input [89:0] in;   
+   
+   output reg [44:0]	line0;
+   output reg [44:0]	line1;   
+   output reg [89:0]	out;      
+   
+   assign  {line0,line1} = in;
+   always @(posedge clk) begin
+      out <= {line0,line1};
+   end
+endmodule