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@@ -10,13 +10,20 @@ module t(/*AUTOARG*/
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);
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input clk;
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logic [7:0] data = 0;
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// Test loop
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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if (data != 15) begin
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data <= data + 8'd1;
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end else begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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bug5782 u_bug5782(.data_out());
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bug5984 u_bug5984(.in(data));
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endmodule
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@@ -29,3 +36,25 @@ module bug5782 (
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data_out = data[7];
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end
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endmodule
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// #5984 inconsistent assignment due to wrong bit range calculation.
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module bug5984 (
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input logic [1:0][3:0] in
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);
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logic [1:0][5:2] internal;
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for (genvar dim1 = 0; dim1 < 2; dim1++) begin
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for (genvar dim2 = 0; dim2 < 4; dim2++) begin
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assign internal[dim1][dim2+2] = in[dim1][dim2];
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end
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end
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for (genvar dim1 = 0; dim1 < 2; dim1++) begin
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for (genvar dim2 = 0; dim2 < 4; dim2++) begin
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always_ff @(negedge internal[dim1][dim2+2]) begin
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$display("%0b", internal[dim1][dim2+2]);
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end
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end
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end
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endmodule
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