Fix Inconsistent assignment error by split-var (#5984) (#5988)

This commit is contained in:
Yutetsu TAKATSUKASA
2025-05-06 05:00:17 -04:00
committed by GitHub
parent fe562d4715
commit 2ed754d5ea
2 changed files with 33 additions and 10 deletions
+31 -2
View File
@@ -10,13 +10,20 @@ module t(/*AUTOARG*/
);
input clk;
logic [7:0] data = 0;
// Test loop
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
if (data != 15) begin
data <= data + 8'd1;
end else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
bug5782 u_bug5782(.data_out());
bug5984 u_bug5984(.in(data));
endmodule
@@ -29,3 +36,25 @@ module bug5782 (
data_out = data[7];
end
endmodule
// #5984 inconsistent assignment due to wrong bit range calculation.
module bug5984 (
input logic [1:0][3:0] in
);
logic [1:0][5:2] internal;
for (genvar dim1 = 0; dim1 < 2; dim1++) begin
for (genvar dim2 = 0; dim2 < 4; dim2++) begin
assign internal[dim1][dim2+2] = in[dim1][dim2];
end
end
for (genvar dim1 = 0; dim1 < 2; dim1++) begin
for (genvar dim2 = 0; dim2 < 4; dim2++) begin
always_ff @(negedge internal[dim1][dim2+2]) begin
$display("%0b", internal[dim1][dim2+2]);
end
end
end
endmodule