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Internals: Make all scheduling region use a single trigger vector. (#6620) 

The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now
it uses a single "extended" trigger vector where the top bits are what
used to be the used bits in the 'pre' trigger vector. Please see the
description above `TriggerKit`. Also move the extra triggers from the
low end to the high end in the trigger vectors.
This commit is contained in:
Geza Lore 2025-11-01 16:43:20 +01:00 committed by GitHub
parent e27613ed45
commit 2e502aead8
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17 changed files with 1257 additions and 1482 deletions
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2
docs/gen/ex_DIDNOTCONVERGE_msg.rst
View File

@ -1,5 +1,5 @@
.. comment: generated by t_lint_didnotconverge_bad
.. code-block::
-V{t#,#} 'stl' region trigger index 64 is active: @([hybrid] a)
-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] a)
%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries

115
src/V3Sched.cpp
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@ -392,19 +392,19 @@ void createSettle(AstNetlist* netlistp, AstCFunc* const initFuncp, SenExprBuilde
// Gather the relevant sensitivity expressions and create the trigger kit
const auto& senTreeps = getSenTreesUsedBy({&comb, &hybrid});
const TriggerKit trigKit = TriggerKit::create(netlistp, initFuncp, senExprBulider, senTreeps,
"stl", extraTriggers, true);
const TriggerKit trigKit = TriggerKit::create(netlistp, initFuncp, senExprBulider, {},
senTreeps, "stl", extraTriggers, true);
// Remap sensitivities (comb has none, so only do the hybrid)
remapSensitivities(hybrid, trigKit.map());
remapSensitivities(hybrid, trigKit.mapVec());
// Create the inverse map from trigger ref AstSenTree to original AstSenTree
V3Order::TrigToSenMap trigToSen;
invertAndMergeSenTreeMap(trigToSen, trigKit.map());
invertAndMergeSenTreeMap(trigToSen, trigKit.mapVec());
// First trigger is for pure combinational triggers (first iteration)
AstSenTree* const inputChanged
= trigKit.newTriggerSenTree(trigKit.vscp(), {firstIterationTrigger});
= trigKit.newExtraTriggerSenTree(trigKit.vscp(), firstIterationTrigger);
// Create and the body function
AstCFunc* const stlFuncp = V3Order::order(
@ -473,8 +473,8 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp,
// Gather the relevant sensitivity expressions and create the trigger kit
const auto& senTreeps = getSenTreesUsedBy({&logic});
const TriggerKit trigKit = TriggerKit::create(netlistp, initFuncp, senExprBuilder, senTreeps,
"ico", extraTriggers, false);
const TriggerKit trigKit = TriggerKit::create(netlistp, initFuncp, senExprBuilder, {},
senTreeps, "ico", extraTriggers, false);
if (dpiExportTriggerVscp) {
trigKit.addExtraTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex);
@ -483,19 +483,20 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp,
firstVifMemberTriggerIndex, trigKit);
// Remap sensitivities
remapSensitivities(logic, trigKit.map());
remapSensitivities(logic, trigKit.mapVec());
// Create the inverse map from trigger ref AstSenTree to original AstSenTree
V3Order::TrigToSenMap trigToSen;
invertAndMergeSenTreeMap(trigToSen, trigKit.map());
invertAndMergeSenTreeMap(trigToSen, trigKit.mapVec());
// The trigger top level inputs (first iteration)
AstSenTree* const inputChanged
= trigKit.newTriggerSenTree(trigKit.vscp(), {firstIterationTrigger});
= trigKit.newExtraTriggerSenTree(trigKit.vscp(), firstIterationTrigger);
// The DPI Export trigger
AstSenTree* const dpiExportTriggered
= dpiExportTriggerVscp ? trigKit.newTriggerSenTree(trigKit.vscp(), {dpiExportTriggerIndex})
= dpiExportTriggerVscp
? trigKit.newExtraTriggerSenTree(trigKit.vscp(), dpiExportTriggerIndex)
: nullptr;
const auto& vifTriggeredIco
= virtIfaceTriggers.makeIfaceToSensMap(trigKit, firstVifTriggerIndex, trigKit.vscp());
@ -554,7 +555,6 @@ void createEval(AstNetlist* netlistp, //
AstNode* icoLoop, //
const TriggerKit& trigKit, //
const EvalKit& actKit, //
AstVarScope* preTrigsp, //
const EvalKit& nbaKit, //
const EvalKit& obsKit, //
const EvalKit& reactKit, //
@ -574,13 +574,10 @@ void createEval(AstNetlist* netlistp, //
nullptr,
// Prep statements
[&]() {
// Compute the current 'act' triggers
AstNodeStmt* stmtsp = trigKit.newCompCall();
// Compute the current 'act' triggers - the NBA triggers are the latched value
AstNodeStmt* stmtsp = trigKit.newCompCall(nbaKit.m_vscp);
// Commit trigger awaits from the previous iteration
if (timingCommitp) stmtsp = AstNode::addNext(stmtsp, timingCommitp->makeStmt());
// Compute the 'pre' triggers
stmtsp = AstNode::addNext(
stmtsp, trigKit.newAndNotCall(preTrigsp, actKit.m_vscp, nbaKit.m_vscp));
// Latch the 'act' triggers under the 'nba' triggers
stmtsp = AstNode::addNext(stmtsp, trigKit.newOrIntoCall(nbaKit.m_vscp, actKit.m_vscp));
//
@ -711,7 +708,7 @@ VirtIfaceTriggers::makeIfaceToSensMap(const TriggerKit& trigKit, uint32_t vifTri
AstVarScope* trigVscp) const {
std::map<const AstIface*, AstSenTree*> map;
for (const auto& p : m_ifaceTriggers) {
map.emplace(p.first, trigKit.newTriggerSenTree(trigVscp, {vifTriggerIndex}));
map.emplace(p.first, trigKit.newExtraTriggerSenTree(trigVscp, vifTriggerIndex));
++vifTriggerIndex;
}
return map;
@ -722,12 +719,31 @@ VirtIfaceTriggers::makeMemberToSensMap(const TriggerKit& trigKit, uint32_t vifTr
AstVarScope* trigVscp) const {
IfaceMemberSensMap map;
for (const auto& p : m_memberTriggers) {
map.emplace(p.first, trigKit.newTriggerSenTree(trigVscp, {vifTriggerIndex}));
map.emplace(p.first, trigKit.newExtraTriggerSenTree(trigVscp, vifTriggerIndex));
++vifTriggerIndex;
}
return map;
}
std::unordered_map<const AstSenTree*, AstSenTree*>
cloneMapWithNewTriggerReferences(const std::unordered_map<const AstSenTree*, AstSenTree*>& map,
AstVarScope* vscp) {
AstTopScope* const topScopep = v3Global.rootp()->topScopep();
// Copy map
std::unordered_map<const AstSenTree*, AstSenTree*> newMap{map};
// Replace references in each mapped value with a reference to the given vscp
for (auto& pair : newMap) {
pair.second = pair.second->cloneTree(false);
pair.second->foreach([&](AstVarRef* refp) {
UASSERT_OBJ(refp->access() == VAccess::READ, refp, "Should be read ref");
refp->replaceWith(new AstVarRef{refp->fileline(), vscp, VAccess::READ});
VL_DO_DANGLING(refp->deleteTree(), refp);
});
topScopep->addSenTreesp(pair.second);
}
return newMap;
}
//============================================================================
// Top level entry-point to scheduling
@ -816,7 +832,7 @@ void schedule(AstNetlist* netlistp) {
logicReplicas.m_ico, virtIfaceTriggers);
if (v3Global.opt.stats()) V3Stats::statsStage("sched-create-ico");
// Step 8: Create the pre/act/nba triggers
// Step 8: Create the triggers
AstVarScope* const dpiExportTriggerVscp = netlistp->dpiExportTriggerp();
netlistp->dpiExportTriggerp(nullptr); // Finished with this here
@ -836,14 +852,14 @@ void schedule(AstNetlist* netlistp) {
+ item.m_memberp->name());
}
const auto& senTreeps = getSenTreesUsedBy({&logicRegions.m_pre, //
&logicRegions.m_act, //
const auto& preTreeps = getSenTreesUsedBy({&logicRegions.m_pre});
const auto& senTreeps = getSenTreesUsedBy({&logicRegions.m_act, //
&logicRegions.m_nba, //
&logicRegions.m_obs, //
&logicRegions.m_react, //
&timingKit.m_lbs});
const TriggerKit trigKit = TriggerKit::create(netlistp, staticp, senExprBuilder, senTreeps,
"act", extraTriggers, false);
const TriggerKit trigKit = TriggerKit::create(netlistp, staticp, senExprBuilder, preTreeps,
senTreeps, "act", extraTriggers, false);
// Add post updates from the timing kit
if (timingKit.m_postUpdates) trigKit.compp()->addStmtsp(timingKit.m_postUpdates);
@ -853,30 +869,6 @@ void schedule(AstNetlist* netlistp) {
}
addVirtIfaceTriggerAssignments(virtIfaceTriggers, firstVifTriggerIndex,
firstVifMemberTriggerIndex, trigKit);
AstVarScope* const actTrigVscp = trigKit.vscp();
AstVarScope* const preTrigVscp = trigKit.newTrigVec("pre");
const auto cloneMapWithNewTriggerReferences
= [=](const std::unordered_map<const AstSenTree*, AstSenTree*>& map, AstVarScope* vscp) {
// Copy map
auto newMap{map};
// Replace references in each mapped value with a reference to the given vscp
for (auto& pair : newMap) {
pair.second = pair.second->cloneTree(false);
pair.second->foreach([&](AstVarRef* refp) {
UASSERT_OBJ(refp->varScopep() == actTrigVscp, refp, "Unexpected reference");
UASSERT_OBJ(refp->access() == VAccess::READ, refp, "Should be read ref");
refp->replaceWith(new AstVarRef{refp->fileline(), vscp, VAccess::READ});
VL_DO_DANGLING(refp->deleteTree(), refp);
});
topScopep->addSenTreesp(pair.second);
}
return newMap;
};
const auto& actTrigMap = trigKit.map();
const auto preTrigMap = cloneMapWithNewTriggerReferences(actTrigMap, preTrigVscp);
if (v3Global.opt.stats()) V3Stats::statsStage("sched-create-triggers");
// Note: Experiments so far show that running the Act (or Ico) regions on
@ -887,20 +879,22 @@ void schedule(AstNetlist* netlistp) {
// Step 9: Create the 'act' region evaluation function
// Remap sensitivities of the input logic to the triggers
remapSensitivities(logicRegions.m_pre, preTrigMap);
remapSensitivities(logicRegions.m_act, actTrigMap);
remapSensitivities(logicReplicas.m_act, actTrigMap);
remapSensitivities(timingKit.m_lbs, actTrigMap);
const auto& actTimingDomains = timingKit.remapDomains(actTrigMap);
remapSensitivities(logicRegions.m_pre, trigKit.mapPre());
remapSensitivities(logicRegions.m_act, trigKit.mapVec());
remapSensitivities(logicReplicas.m_act, trigKit.mapVec());
remapSensitivities(timingKit.m_lbs, trigKit.mapVec());
const std::map<const AstVarScope*, std::vector<AstSenTree*>> actTimingDomains
= timingKit.remapDomains(trigKit.mapVec());
// Create the inverse map from trigger ref AstSenTree to original AstSenTree
V3Order::TrigToSenMap trigToSenAct;
invertAndMergeSenTreeMap(trigToSenAct, preTrigMap);
invertAndMergeSenTreeMap(trigToSenAct, actTrigMap);
invertAndMergeSenTreeMap(trigToSenAct, trigKit.mapPre());
invertAndMergeSenTreeMap(trigToSenAct, trigKit.mapVec());
// The DPI Export trigger AstSenTree
AstSenTree* const dpiExportTriggeredAct
= dpiExportTriggerVscp ? trigKit.newTriggerSenTree(trigKit.vscp(), {dpiExportTriggerIndex})
= dpiExportTriggerVscp
? trigKit.newExtraTriggerSenTree(trigKit.vscp(), dpiExportTriggerIndex)
: nullptr;
const auto& vifTriggeredAct
@ -930,7 +924,7 @@ void schedule(AstNetlist* netlistp) {
const std::vector<V3Sched::LogicByScope*>& logic) -> EvalKit {
UINFO(2, "Scheduling " << name << " #logic = " << logic.size());
AstVarScope* const trigVscp = trigKit.newTrigVec(name);
const auto trigMap = cloneMapWithNewTriggerReferences(actTrigMap, trigVscp);
const auto trigMap = cloneMapWithNewTriggerReferences(trigKit.mapVec(), trigVscp);
// Remap sensitivities of the input logic to the triggers
for (LogicByScope* lbs : logic) remapSensitivities(*lbs, trigMap);
@ -939,7 +933,8 @@ void schedule(AstNetlist* netlistp) {
invertAndMergeSenTreeMap(trigToSen, trigMap);
AstSenTree* const dpiExportTriggered
= dpiExportTriggerVscp ? trigKit.newTriggerSenTree(trigVscp, {dpiExportTriggerIndex})
= dpiExportTriggerVscp
? trigKit.newExtraTriggerSenTree(trigVscp, dpiExportTriggerIndex)
: nullptr;
const auto& vifTriggered
= virtIfaceTriggers.makeIfaceToSensMap(trigKit, firstVifTriggerIndex, trigVscp);
@ -991,8 +986,8 @@ void schedule(AstNetlist* netlistp) {
auto* const postponedFuncp = createPostponed(netlistp, logicClasses);
// Step 14: Bolt it all together to create the '_eval' function
createEval(netlistp, icoLoopp, trigKit, actKit, preTrigVscp, nbaKit, obsKit, reactKit,
postponedFuncp, timingKit);
createEval(netlistp, icoLoopp, trigKit, actKit, nbaKit, obsKit, reactKit, postponedFuncp,
timingKit);
// Haven't split static initializer yet
util::splitCheck(staticp);

112
src/V3Sched.h
View File

@ -128,7 +128,61 @@ struct LogicReplicas final {
LogicReplicas& operator=(LogicReplicas&&) = default;
};
// A TriggerKit holds all the components related to a trigger vector
// A TriggerKit holds all the components related to a scheduling region triggers
//
// Each piece of code is executed when some trigger bits are set. There is no
// code after scheduling which is not conditional on at least one trigger bit.
//
// There are 3 different kinds of triggers
// 1. "Sense" triggers, which correspond to a unique SenItem in the design
// 2. "Extra" triggers, which represent non SenItem based conditions
// 3. "Pre" triggers, which are only used in the 'act' region. These are a copy
// of some of the "Sense" triggers but only ever fire during one evaluation
// of the 'act' loop. They are used for executing AlwaysPre block that
// reside in the 'act' region. (AlwaysPre in 'nba' use the "Sense" triggers.)
//
// All trigger bits are stored in an unpacked array of fixed sized words, which
// is informally referred to in various places as the "trigger vector".
// There is only one trigger vector for each eval loop (~scheduling region).
//
// The organization of the trigger vector (array) is shown here, LSB on the
// right, MSB on the left. There are 4 main sections:
//
// | <- bit N-1 bit 0 -> |
// +--------------------+----------------+----------------------------------+--------------------+
// | Pre triggers | Extra triggers | Sense triggers | Pre Sense triggers |
// +--------------------+----------------+----------------------------------+--------------------+
// | 'pre' | 'vec' |
//
// The section labelled "Pre Sense triggers" contains regular "Sense" triggers
// that are also duplicated in the "Pre triggers" section the first time they
// fire.
//
// The "Sense triggers" section contains the rest of the "Sense" triggers that
// do not need a copy in "Pre triggers".
//
// The "Sense triggers" and "Pre Sense triggers" together contain all "Sense"
// triggers described in point 1 above. "Extra triggers" contains the
// non-SenItem based additional conditions described in point 2, and the
// "Per triggers" section contains the "Pre" triggers described in point 3.
//
// All 4 sections in the trigger vector are padded to contain a whole word
// worth of bits (padding bits are always zero). Any one of the 4 sections
// can be empty, but "Pre triggers" and "Pre Sense triggers" are always the
// same size.
//
// The portion holding the Sense triggers and Extra triggers is referred to
// in various places as the 'vec' part, and is also informally referred to as
// the trigger vector.
//
// The portion holding the Pre trigger is named 'pre'
//
// The combination of 'pre' + 'vec' is the "extended trigger vector" referred
// to as 'ext' in various places.
//
// In realistic designs there are often no "Pre" triggers, and only a few
// "Extra" triggers, with "Sense" triggers taking up the bulk of the bits.
//
class TriggerKit final {
// Triggers are storead as an UnpackedArray with a fixed word size
static constexpr uint32_t WORD_SIZE_LOG2 = 6; // 64-bits / VL_QUADSIZE
@ -136,37 +190,51 @@ class TriggerKit final {
const std::string m_name; // TriggerKit name
const bool m_slow; // TriggerKit is for schedulign 'slow' code
const uint32_t m_nWords; // Number of word in trigger vector
const uint32_t m_nSenseWords; // Number of words for Sense triggers
const uint32_t m_nExtraWords; // Number of words for Extra triggers
const uint32_t m_nPreWords; // Number of words for 'pre' part
const uint32_t m_nVecWords = m_nSenseWords + m_nExtraWords; // Number of words in 'vec' part
// Data type of a single trigger word
AstNodeDType* m_wordDTypep = nullptr;
// Data type of a trigger vector
AstNodeDType* m_trigDTypep = nullptr;
// The AstVarScope representing the trigger vector
// Data type of a trigger vector holding one copy of all triggers
AstUnpackArrayDType* m_trigVecDTypep = nullptr;
// Data type of an extended trigger vector holding one copy of all triggers
// + additional copy of 'pre' triggers
AstUnpackArrayDType* m_trigExtDTypep = nullptr;
// The AstVarScope representing the extended trigger vector
AstVarScope* m_vscp = nullptr;
// The AstCFunc that computes the current active triggers
AstCFunc* m_compp = nullptr;
// The AstCFunc that dumps the current active triggers
// The AstCFunc that dumps a trigger vector
AstCFunc* m_dumpp = nullptr;
// The AstCFunc that dumps an exended trigger vector - create lazily
mutable AstCFunc* m_dumpExtp = nullptr;
// The AstCFunc testing if a trigger vector has any bits set - create lazily
mutable AstCFunc* m_anySetp = nullptr;
// The AstCFunc setting a tigger vector to (_ & ~_) of 2 other trigger vectors - create lazily
mutable AstCFunc* m_andNotp = nullptr;
mutable AstCFunc* m_anySetVecp = nullptr;
mutable AstCFunc* m_anySetExtp = nullptr;
// The AstCFunc setting bits in a trigger vector that are set in another - create lazily
mutable AstCFunc* m_orIntop = nullptr;
mutable AstCFunc* m_orIntoVecp = nullptr;
mutable AstCFunc* m_orIntoExtp = nullptr;
// The AstCFunc setting a trigger vector to all zeroes - create lazily
mutable AstCFunc* m_clearp = nullptr;
// The map from input sensitivity list to trigger sensitivity list
std::unordered_map<const AstSenTree*, AstSenTree*> m_map;
// The map from 'pre' input SenTree to trigger SenTree
std::unordered_map<const AstSenTree*, AstSenTree*> m_mapPre;
// The map from other input SenTree to trigger SenTree
std::unordered_map<const AstSenTree*, AstSenTree*> m_mapVec;
// Methods to lazy construct functions processing trigger vectors
AstCFunc* createAndNotFunc() const;
AstCFunc* createAnySetFunc() const;
AstCFunc* createDumpExtFunc() const;
AstCFunc* createAnySetFunc(AstUnpackArrayDType* const dtypep) const;
AstCFunc* createClearFunc() const;
AstCFunc* createOrIntoFunc() const;
AstCFunc* createOrIntoFunc(AstUnpackArrayDType* const iDtypep) const;
TriggerKit(const std::string& name, bool slow, uint32_t nWords);
// Create an AstSenTree that is sensitive to the given trigger indices
AstSenTree* newTriggerSenTree(AstVarScope* vscp, const std::vector<uint32_t>& indices) const;
TriggerKit(const std::string& name, bool slow, uint32_t nSenseWords, uint32_t nExtraWords,
uint32_t nPreWords);
VL_UNCOPYABLE(TriggerKit);
TriggerKit& operator=(TriggerKit&&) = delete;
@ -195,6 +263,7 @@ public:
static TriggerKit create(AstNetlist* netlistp, //
AstCFunc* const initFuncp, //
SenExprBuilder& senExprBuilder, //
const std::vector<const AstSenTree*>& preTreeps, //
const std::vector<const AstSenTree*>& senTreeps, //
const string& name, //
const ExtraTriggers& extraTriggers, //
@ -203,7 +272,8 @@ public:
// ACCESSORS
AstVarScope* vscp() const { return m_vscp; }
AstCFunc* compp() const { return m_compp; }
const std::unordered_map<const AstSenTree*, AstSenTree*>& map() const { return m_map; }
const std::unordered_map<const AstSenTree*, AstSenTree*>& mapPre() const { return m_mapPre; }
const std::unordered_map<const AstSenTree*, AstSenTree*>& mapVec() const { return m_mapVec; }
// Helpers for code generation - lazy construct relevant functions
AstNodeStmt* newAndNotCall(AstVarScope* op, AstVarScope* ap, AstVarScope* bp) const;
@ -211,13 +281,13 @@ public:
AstNodeStmt* newClearCall(AstVarScope* vscp) const;
AstNodeStmt* newOrIntoCall(AstVarScope* op, AstVarScope* ip) const;
// Helpers for code generation
AstNodeStmt* newCompCall() const;
AstNodeStmt* newCompCall(AstVarScope* vscp = nullptr) const;
AstNodeStmt* newDumpCall(AstVarScope* vscp, const std::string& tag, bool debugOnly) const;
// Create a new trigger vector - might return nullptr if there are no triggers
// Create a new (non-extended) trigger vector - might return nullptr if there are no triggers
AstVarScope* newTrigVec(const std::string& name) const;
// Create an AstSenTree that is sensitive to the given trigger indices
AstSenTree* newTriggerSenTree(AstVarScope* vscp, const std::vector<uint32_t>& indices) const;
// Create an AstSenTree that is sensitive to the given Extra trigger
AstSenTree* newExtraTriggerSenTree(AstVarScope* vscp, uint32_t index) const;
// Set then extra trigger bit at 'index' to the value of 'vscp', then set 'vscp' to 0
void addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index) const;

395
src/V3SchedTrigger.cpp
View File

@ -52,6 +52,7 @@ AstVarScope* newLocal(AstCFunc* funcp, AstNodeDType* dtypep, const std::string&
AstScope* const scopep = funcp->scopep();
AstVar* const varp = new AstVar{flp, VVarType::BLOCKTEMP, name, dtypep};
varp->funcLocal(true);
varp->noReset(true);
funcp->addVarsp(varp);
AstVarScope* const vscp = new AstVarScope{flp, scopep, varp};
scopep->addVarsp(vscp);
@ -60,62 +61,113 @@ AstVarScope* newLocal(AstCFunc* funcp, AstNodeDType* dtypep, const std::string&
} // namespace
AstCFunc* TriggerKit::createAndNotFunc() const {
AstCFunc* TriggerKit::createDumpExtFunc() const {
UASSERT(m_nPreWords, "Just call the regular dumping function if there are no pre triggers");
AstNetlist* const netlistp = v3Global.rootp();
FileLine* const flp = netlistp->topScopep()->fileline();
AstNodeDType* const u32DTypep = netlistp->findUInt32DType();
AstNodeDType* const strDtypep = netlistp->findStringDType();
// Create the function
AstCFunc* const funcp = util::makeSubFunction(netlistp, "_trigger_andNot__" + m_name, m_slow);
// Dumping function always slow
const std::string name = "_dump_triggers__" + m_name + "_ext";
AstCFunc* const funcp = util::makeSubFunction(netlistp, name, true);
funcp->isStatic(true);
funcp->ifdef("VL_DEBUG");
// Add arguments
AstVarScope* const oVscp = newArgument(funcp, m_trigDTypep, "out", VDirection::OUTPUT);
AstVarScope* const aVscp = newArgument(funcp, m_trigDTypep, "inA", VDirection::CONSTREF);
AstVarScope* const bVscp = newArgument(funcp, m_trigDTypep, "inB", VDirection::CONSTREF);
// Add loop counter variable
AstVarScope* const nVscp
= newLocal(funcp, netlistp->findBitDType(32, 32, VSigning::UNSIGNED), "n");
nVscp->varp()->noReset(true);
// Add argument
AstVarScope* const eVscp = newArgument(funcp, m_trigExtDTypep, "ext", VDirection::CONSTREF);
AstVarScope* const tVscp = newArgument(funcp, strDtypep, "tag", VDirection::CONSTREF);
// Creates read/write reference
const auto rd = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::READ}; };
const auto wr = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::WRITE}; };
// Function body
// This is a slow function, only for dumping, so we can just copy to locals
// Copy the vec part, dump it
{
AstVarScope* const vVscp = newLocal(funcp, m_trigVecDTypep, "vec");
AstVarScope* const iVscp = newLocal(funcp, u32DTypep, "i");
funcp->addStmtsp(util::setVar(iVscp, 0));
// Add loop
AstLoop* const loopp = new AstLoop{flp};
funcp->addStmtsp(util::setVar(nVscp, 0));
funcp->addStmtsp(loopp);
// Loop body
AstNodeExpr* const lhsp = new AstArraySel{flp, wr(oVscp), rd(nVscp)};
AstNodeExpr* const aWordp = new AstArraySel{flp, rd(aVscp), rd(nVscp)};
AstNodeExpr* const bWordp = new AstArraySel{flp, rd(bVscp), rd(nVscp)};
AstNodeExpr* const rhsp = new AstAnd{flp, aWordp, new AstNot{flp, bWordp}};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nWords};
AstNodeExpr* const lhsp = new AstArraySel{flp, wr(vVscp), rd(iVscp)};
AstNodeExpr* const rhsp = new AstArraySel{flp, rd(eVscp), rd(iVscp)};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nVecWords};
loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
loopp->addStmtsp(util::incrementVar(nVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}});
loopp->addStmtsp(util::incrementVar(iVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(iVscp), limp}});
// Use the vec dumping function
AstCCall* const callp = new AstCCall{flp, m_dumpp};
callp->dtypeSetVoid();
callp->addArgsp(rd(vVscp));
callp->addArgsp(rd(tVscp));
funcp->addStmtsp(callp->makeStmt());
}
// Copy the pre part, zero top bits, dump it
{
AstVarScope* const pVscp = newLocal(funcp, m_trigVecDTypep, "pre");
AstVarScope* const jVscp = newLocal(funcp, u32DTypep, "j");
funcp->addStmtsp(util::setVar(jVscp, 0));
// Copy pre words
{
// Add loop
AstLoop* const loopp = new AstLoop{flp};
funcp->addStmtsp(loopp);
// Loop body
AstNodeExpr* const lhsp = new AstArraySel{flp, wr(pVscp), rd(jVscp)};
AstNodeExpr* const rhsp = new AstArraySel{flp, rd(eVscp), rd(jVscp)};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nPreWords};
loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
loopp->addStmtsp(util::incrementVar(jVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(jVscp), limp}});
}
// Zero the rest
{
// Add loop - copy
AstLoop* const loopp = new AstLoop{flp};
funcp->addStmtsp(loopp);
// Loop body
AstNodeExpr* const lhsp = new AstArraySel{flp, wr(pVscp), rd(jVscp)};
AstNodeExpr* const rhsp = new AstConst{flp, AstConst::DTyped{}, m_wordDTypep};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nVecWords};
loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
loopp->addStmtsp(util::incrementVar(jVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(jVscp), limp}});
}
// Use the vec dumping function
AstCCall* const callp = new AstCCall{flp, m_dumpp};
callp->dtypeSetVoid();
callp->addArgsp(rd(pVscp));
callp->addArgsp(
new AstConcatN{flp, rd(tVscp), new AstConst{flp, AstConst::String{}, " pre"}});
funcp->addStmtsp(callp->makeStmt());
}
// Done
return funcp;
}
AstCFunc* TriggerKit::createAnySetFunc() const {
AstCFunc* TriggerKit::createAnySetFunc(AstUnpackArrayDType* const dtypep) const {
AstNetlist* const netlistp = v3Global.rootp();
FileLine* const flp = netlistp->topScopep()->fileline();
AstNodeDType* const u32DTypep = netlistp->findUInt32DType();
// Create function
AstCFunc* const funcp = util::makeSubFunction(netlistp, "_trigger_anySet__" + m_name, m_slow);
std::string name = "_trigger_anySet__" + m_name;
name += dtypep == m_trigVecDTypep ? "" : "_ext";
AstCFunc* const funcp = util::makeSubFunction(netlistp, name, m_slow);
funcp->isStatic(true);
funcp->rtnType("bool");
// Add argument
AstVarScope* const iVscp = newArgument(funcp, m_trigDTypep, "in", VDirection::CONSTREF);
AstVarScope* const iVscp = newArgument(funcp, dtypep, "in", VDirection::CONSTREF);
// Add loop counter variable
AstVarScope* const nVscp
= newLocal(funcp, netlistp->findBitDType(32, 32, VSigning::UNSIGNED), "n");
nVscp->varp()->noReset(true);
AstVarScope* const nVscp = newLocal(funcp, u32DTypep, "n");
// Creates read reference
const auto rd = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::READ}; };
@ -127,9 +179,10 @@ AstCFunc* TriggerKit::createAnySetFunc() const {
funcp->addStmtsp(new AstCReturn{flp, new AstConst{flp, AstConst::BitFalse{}}});
// Loop body
const uint32_t nWords = dtypep->elementsConst();
AstNodeExpr* const condp = new AstArraySel{flp, rd(iVscp), rd(nVscp)};
AstNodeStmt* const thenp = new AstCReturn{flp, new AstConst{flp, AstConst::BitTrue{}}};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nWords};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, nWords};
loopp->addStmtsp(new AstIf{flp, condp, thenp});
loopp->addStmtsp(util::incrementVar(nVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}});
@ -140,18 +193,17 @@ AstCFunc* TriggerKit::createAnySetFunc() const {
AstCFunc* TriggerKit::createClearFunc() const {
AstNetlist* const netlistp = v3Global.rootp();
FileLine* const flp = netlistp->topScopep()->fileline();
AstNodeDType* const u32DTypep = netlistp->findUInt32DType();
// Create function
AstCFunc* const funcp = util::makeSubFunction(netlistp, "_trigger_clear__" + m_name, m_slow);
funcp->isStatic(true);
// Add arguments
AstVarScope* const oVscp = newArgument(funcp, m_trigDTypep, "out", VDirection::OUTPUT);
AstVarScope* const oVscp = newArgument(funcp, m_trigVecDTypep, "out", VDirection::OUTPUT);
// Add loop counter variable
AstVarScope* const nVscp
= newLocal(funcp, netlistp->findBitDType(32, 32, VSigning::UNSIGNED), "n");
nVscp->varp()->noReset(true);
AstVarScope* const nVscp = newLocal(funcp, u32DTypep, "n");
// Creates read/write reference
const auto rd = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::READ}; };
@ -165,7 +217,7 @@ AstCFunc* TriggerKit::createClearFunc() const {
// Loop body
AstNodeExpr* const lhsp = new AstArraySel{flp, wr(oVscp), rd(nVscp)};
AstNodeExpr* const rhsp = new AstConst{flp, AstConst::DTyped{}, m_wordDTypep};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nWords};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nVecWords};
loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
loopp->addStmtsp(util::incrementVar(nVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}});
@ -173,22 +225,23 @@ AstCFunc* TriggerKit::createClearFunc() const {
// Done
return funcp;
}
AstCFunc* TriggerKit::createOrIntoFunc() const {
AstCFunc* TriggerKit::createOrIntoFunc(AstUnpackArrayDType* const iDtypep) const {
AstNetlist* const netlistp = v3Global.rootp();
FileLine* const flp = netlistp->topScopep()->fileline();
AstNodeDType* const u32DTypep = netlistp->findUInt32DType();
// Create function
AstCFunc* const funcp = util::makeSubFunction(netlistp, "_trigger_orInto__" + m_name, m_slow);
std::string name = "_trigger_orInto__" + m_name;
name += iDtypep == m_trigVecDTypep ? "" : "_ext";
AstCFunc* const funcp = util::makeSubFunction(netlistp, name, m_slow);
funcp->isStatic(true);
// Add arguments
AstVarScope* const oVscp = newArgument(funcp, m_trigDTypep, "out", VDirection::INOUT);
AstVarScope* const iVscp = newArgument(funcp, m_trigDTypep, "in", VDirection::CONSTREF);
AstVarScope* const oVscp = newArgument(funcp, m_trigVecDTypep, "out", VDirection::INOUT);
AstVarScope* const iVscp = newArgument(funcp, iDtypep, "in", VDirection::CONSTREF);
// Add loop counter variable
AstVarScope* const nVscp
= newLocal(funcp, netlistp->findBitDType(32, 32, VSigning::UNSIGNED), "n");
nVscp->varp()->noReset(true);
AstVarScope* const nVscp = newLocal(funcp, u32DTypep, "n");
// Creates read/write reference
const auto rd = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::READ}; };
@ -204,7 +257,7 @@ AstCFunc* TriggerKit::createOrIntoFunc() const {
AstNodeExpr* const oWordp = new AstArraySel{flp, rd(oVscp), rd(nVscp)};
AstNodeExpr* const iWordp = new AstArraySel{flp, rd(iVscp), rd(nVscp)};
AstNodeExpr* const rhsp = new AstOr{flp, oWordp, iWordp};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nWords};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nVecWords};
loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
loopp->addStmtsp(util::incrementVar(nVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}});
@ -213,32 +266,28 @@ AstCFunc* TriggerKit::createOrIntoFunc() const {
return funcp;
}
AstNodeStmt* TriggerKit::newAndNotCall(AstVarScope* const oVscp, //
AstVarScope* const aVscp, //
AstVarScope* const bVscp) const {
if (!m_nWords) return nullptr;
if (!m_andNotp) m_andNotp = createAndNotFunc();
FileLine* const flp = v3Global.rootp()->topScopep()->fileline();
AstCCall* const callp = new AstCCall{flp, m_andNotp};
callp->addArgsp(new AstVarRef{flp, oVscp, VAccess::WRITE});
callp->addArgsp(new AstVarRef{flp, aVscp, VAccess::READ});
callp->addArgsp(new AstVarRef{flp, bVscp, VAccess::READ});
callp->dtypeSetVoid();
return callp->makeStmt();
}
AstNodeExpr* TriggerKit::newAnySetCall(AstVarScope* const vscp) const {
FileLine* const flp = v3Global.rootp()->topScopep()->fileline();
if (!m_nWords) return new AstConst{flp, AstConst::BitFalse{}};
if (!m_nVecWords) return new AstConst{flp, AstConst::BitFalse{}};
if (!m_anySetp) m_anySetp = createAnySetFunc();
AstCCall* const callp = new AstCCall{flp, m_anySetp};
AstCFunc* funcp = nullptr;
if (vscp->dtypep() == m_trigVecDTypep) {
if (!m_anySetVecp) m_anySetVecp = createAnySetFunc(m_trigVecDTypep);
funcp = m_anySetVecp;
} else if (vscp->dtypep() == m_trigExtDTypep) {
if (!m_anySetExtp) m_anySetExtp = createAnySetFunc(m_trigExtDTypep);
funcp = m_anySetExtp;
} else {
vscp->v3fatalSrc("Bad trigger vector type");
}
AstCCall* const callp = new AstCCall{flp, funcp};
callp->addArgsp(new AstVarRef{flp, vscp, VAccess::WRITE});
callp->dtypeSetBit();
return callp;
}
AstNodeStmt* TriggerKit::newClearCall(AstVarScope* const vscp) const {
if (!m_nWords) return nullptr;
if (!m_nVecWords) return nullptr;
UASSERT_OBJ(vscp->dtypep() == m_trigVecDTypep, vscp, "Bad trigger vector type");
if (!m_clearp) m_clearp = createClearFunc();
FileLine* const flp = v3Global.rootp()->topScopep()->fileline();
AstCCall* const callp = new AstCCall{flp, m_clearp};
@ -247,27 +296,51 @@ AstNodeStmt* TriggerKit::newClearCall(AstVarScope* const vscp) const {
return callp->makeStmt();
}
AstNodeStmt* TriggerKit::newOrIntoCall(AstVarScope* const oVscp, AstVarScope* const iVscp) const {
if (!m_nWords) return nullptr;
if (!m_orIntop) m_orIntop = createOrIntoFunc();
if (!m_nVecWords) return nullptr;
UASSERT_OBJ(oVscp->dtypep() == m_trigVecDTypep, oVscp, "Bad trigger vector type");
AstCFunc* funcp = nullptr;
if (iVscp->dtypep() == m_trigVecDTypep) {
if (!m_orIntoVecp) m_orIntoVecp = createOrIntoFunc(m_trigVecDTypep);
funcp = m_orIntoVecp;
} else if (iVscp->dtypep() == m_trigExtDTypep) {
if (!m_orIntoExtp) m_orIntoExtp = createOrIntoFunc(m_trigExtDTypep);
funcp = m_orIntoExtp;
} else {
iVscp->v3fatalSrc("Bad trigger vector type");
}
FileLine* const flp = v3Global.rootp()->topScopep()->fileline();
AstCCall* const callp = new AstCCall{flp, m_orIntop};
AstCCall* const callp = new AstCCall{flp, funcp};
callp->addArgsp(new AstVarRef{flp, oVscp, VAccess::WRITE});
callp->addArgsp(new AstVarRef{flp, iVscp, VAccess::READ});
callp->dtypeSetVoid();
return callp->makeStmt();
}
AstNodeStmt* TriggerKit::newCompCall() const {
if (!m_nWords) return nullptr;
return util::callVoidFunc(m_compp);
AstNodeStmt* TriggerKit::newCompCall(AstVarScope* vscp) const {
if (!m_nVecWords) return nullptr;
// If there are pre triggers, we need the argument
UASSERT(!m_nPreWords || vscp, "Need latched values for pre trigger compute");
FileLine* const flp = v3Global.rootp()->topScopep()->fileline();
AstCCall* const callp = new AstCCall{flp, m_compp};
if (m_nPreWords) callp->addArgsp(new AstVarRef{flp, vscp, VAccess::READ});
callp->dtypeSetVoid();
return callp->makeStmt();
}
AstNodeStmt* TriggerKit::newDumpCall(AstVarScope* const vscp, const std::string& tag,
bool debugOnly) const {
if (!m_nVecWords) return nullptr;
AstCFunc* funcp = nullptr;
if (vscp->dtypep() == m_trigVecDTypep) {
funcp = m_dumpp;
} else if (vscp->dtypep() == m_trigExtDTypep) {
if (!m_dumpExtp) m_dumpExtp = createDumpExtFunc();
funcp = m_dumpExtp;
} else {
vscp->v3fatalSrc("Bad trigger vector type");
}
FileLine* const flp = v3Global.rootp()->topScopep()->fileline();
if (!m_nWords) return new AstComment{flp, "No triggers - dump"};
AstCCall* const callp = new AstCCall{flp, m_dumpp};
AstCCall* const callp = new AstCCall{flp, funcp};
callp->addArgsp(new AstVarRef{flp, vscp, VAccess::READ});
callp->addArgsp(new AstConst{flp, AstConst::String{}, tag});
callp->dtypeSetVoid();
@ -285,9 +358,9 @@ AstNodeStmt* TriggerKit::newDumpCall(AstVarScope* const vscp, const std::string&
}
AstVarScope* TriggerKit::newTrigVec(const std::string& name) const {
if (!m_trigDTypep) return nullptr;
if (!m_nVecWords) return nullptr;
AstScope* const scopep = v3Global.rootp()->topScopep()->scopep();
return scopep->createTemp("__V" + name + "Triggered", m_trigDTypep);
return scopep->createTemp("__V" + name + "Triggered", m_trigVecDTypep);
}
AstSenTree* TriggerKit::newTriggerSenTree(AstVarScope* const vscp,
@ -299,7 +372,7 @@ AstSenTree* TriggerKit::newTriggerSenTree(AstVarScope* const vscp,
AstSenTree* const senTreep = new AstSenTree{flp, nullptr};
topScopep->addSenTreesp(senTreep);
for (const uint32_t index : indices) {
UASSERT(index <= m_nWords * WORD_SIZE, "Invalid trigger index");
UASSERT(index <= (m_nVecWords + m_nPreWords) * WORD_SIZE, "Invalid trigger index");
const uint32_t wordIndex = index / WORD_SIZE;
const uint32_t bitIndex = index % WORD_SIZE;
AstVarRef* const refp = new AstVarRef{flp, vscp, VAccess::READ};
@ -314,7 +387,13 @@ AstSenTree* TriggerKit::newTriggerSenTree(AstVarScope* const vscp,
return senTreep;
}
AstSenTree* TriggerKit::newExtraTriggerSenTree(AstVarScope* vscp, uint32_t index) const {
UASSERT(index <= m_nExtraWords * WORD_SIZE, "Invalid external trigger index");
return newTriggerSenTree(vscp, {index + m_nSenseWords * WORD_SIZE});
}
void TriggerKit::addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index) const {
index += m_nSenseWords * WORD_SIZE;
const uint32_t wordIndex = index / WORD_SIZE;
const uint32_t bitIndex = index % WORD_SIZE;
FileLine* const flp = vscp->fileline();
@ -333,24 +412,35 @@ void TriggerKit::addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index) co
m_compp->stmtsp()->addHereThisAsNext(setp);
}
TriggerKit::TriggerKit(const std::string& name, bool slow, uint32_t nWords)
TriggerKit::TriggerKit(const std::string& name, bool slow, uint32_t nSenseWords,
uint32_t nExtraWords, uint32_t nPreWords)
: m_name{name}
, m_slow{slow}
, m_nWords{nWords} {
, m_nSenseWords{nSenseWords}
, m_nExtraWords{nExtraWords}
, m_nPreWords{nPreWords} {
// If no triggers, we don't need to generate anything
if (!nWords) return;
if (!m_nVecWords) return;
// Othewise construc the parts of the kit
AstNetlist* const netlistp = v3Global.rootp();
AstScope* const scopep = netlistp->topScopep()->scopep();
FileLine* const flp = scopep->fileline();
// Data type of a single trigger word
m_wordDTypep = netlistp->findBitDType(WORD_SIZE, WORD_SIZE, VSigning::UNSIGNED);
// Data type of a trigger vector
AstRange* const rangep = new AstRange{flp, static_cast<int>(m_nWords - 1), 0};
m_trigDTypep = new AstUnpackArrayDType{flp, m_wordDTypep, rangep};
netlistp->typeTablep()->addTypesp(m_trigDTypep);
// The AstVarScope representing the trigger vector
m_vscp = scopep->createTemp("__V" + m_name + "Triggered", m_trigDTypep);
// Data type of trigger vector
AstRange* const rp = new AstRange{flp, static_cast<int>(m_nVecWords - 1), 0};
m_trigVecDTypep = new AstUnpackArrayDType{flp, m_wordDTypep, rp};
netlistp->typeTablep()->addTypesp(m_trigVecDTypep);
// Data type of extended trigger vector, which only differs if there are pre triggers
if (m_nPreWords) {
AstRange* const ep = new AstRange{flp, static_cast<int>(m_nVecWords + m_nPreWords - 1), 0};
m_trigExtDTypep = new AstUnpackArrayDType{flp, m_wordDTypep, ep};
netlistp->typeTablep()->addTypesp(m_trigExtDTypep);
} else {
m_trigExtDTypep = m_trigVecDTypep;
}
// The AstVarScope representing the extended trigger vector
m_vscp = scopep->createTemp("__V" + m_name + "Triggered", m_trigExtDTypep);
m_vscp->varp()->isInternal(true);
// The trigger computation function
m_compp = util::makeSubFunction(netlistp, "_eval_triggers__" + m_name, m_slow);
@ -363,47 +453,74 @@ TriggerKit::TriggerKit(const std::string& name, bool slow, uint32_t nWords)
TriggerKit TriggerKit::create(AstNetlist* netlistp, //
AstCFunc* const initFuncp, //
SenExprBuilder& senExprBuilder, //
const std::vector<const AstSenTree*>& preTreeps, //
const std::vector<const AstSenTree*>& senTreeps, //
const string& name, //
const ExtraTriggers& extraTriggers, //
bool slow) {
FileLine* const flp = netlistp->topScopep()->fileline();
// Need to gather all the unique SenItems under the given SenTrees
// Number of extra triggers, rounded up to a full word. These occupy the lowest words.
const uint32_t nExtraTriggers = vlstd::roundUpToMultipleOf<WORD_SIZE>(extraTriggers.size());
const uint32_t nExtraWords = nExtraTriggers / WORD_SIZE;
// Gather all the unique SenItems under the SenTrees
// List of unique SenItems used by all 'senTreeps'
std::vector<const AstSenItem*> senItemps;
// Map from SenItem to tigger bit standing for that SenItem. There might
// be duplicate SenItems, we map all of them to the same index.
std::unordered_map<VNRef<const AstSenItem>, size_t> senItem2TrigIdx;
// Process the 'pre' trees first, so they are at the begining of the vector
for (const AstSenTree* const senTreep : preTreeps) {
for (const AstSenItem *itemp = senTreep->sensesp(), *nextp; itemp; itemp = nextp) {
nextp = VN_AS(itemp->nextp(), SenItem);
UASSERT_OBJ(itemp->isClocked() || itemp->isHybrid(), itemp,
"Cannot create trigger expression for non-clocked sensitivity");
const auto pair = senItem2TrigIdx.emplace(*itemp, senItemps.size());
if (pair.second) senItemps.push_back(itemp);
}
}
const uint32_t nPreSenItems = senItemps.size();
V3Stats::addStat("Scheduling, '" + name + "' pre triggers", nPreSenItems);
// Number of pre triggers, rounded up to a full word.
const uint32_t nPreTriggers = vlstd::roundUpToMultipleOf<WORD_SIZE>(senItemps.size());
// Pad 'senItemps' to nSenseTriggers with nullptr
senItemps.resize(nPreTriggers);
// Number of words for pre triggers
const uint32_t nPreWords = nPreTriggers / WORD_SIZE;
// Process the rest of the trees
for (const AstSenTree* const senTreep : senTreeps) {
for (const AstSenItem *itemp = senTreep->sensesp(), *nextp; itemp; itemp = nextp) {
nextp = VN_AS(itemp->nextp(), SenItem);
UASSERT_OBJ(itemp->isClocked() || itemp->isHybrid(), itemp,
"Cannot create trigger expression for non-clocked sensitivity");
const auto pair = senItem2TrigIdx.emplace(*itemp, nExtraTriggers + senItemps.size());
const auto pair = senItem2TrigIdx.emplace(*itemp, senItemps.size());
if (pair.second) senItemps.push_back(itemp);
}
}
UASSERT(senItemps.size() == senItem2TrigIdx.size(), "Inconsitent SenItem to trigger map");
const uint32_t nSenItems = senItemps.size() - nPreTriggers;
V3Stats::addStat("Scheduling, '" + name + "' sense triggers", nSenItems + nPreSenItems);
// Number of sense triggers, rounded up to a full word
const uint32_t nSenseTriggers = vlstd::roundUpToMultipleOf<WORD_SIZE>(senItemps.size());
// Total number of trigger words
const uint32_t nWords = (nSenseTriggers / WORD_SIZE) + nExtraWords;
// Pad 'senItemps' to nSenseTriggers with nullptr
senItemps.resize(nSenseTriggers);
// Number of words sense triggers (inclued pre)
const uint32_t nSenseWords = nSenseTriggers / WORD_SIZE;
// We can now construct the trigger kit - this construct all items that will be kept
TriggerKit kit{name, slow, nWords};
// Allocate space for the extra triggers
V3Stats::addStat("Scheduling, '" + name + "' extra triggers", extraTriggers.size());
// Number of extra triggers, rounded up to a full word.
const uint32_t nExtraTriggers = vlstd::roundUpToMultipleOf<WORD_SIZE>(extraTriggers.size());
const uint32_t nExtraWords = nExtraTriggers / WORD_SIZE;
// We can now construct the trigger kit - this constructs all items that will be kept
TriggerKit kit{name, slow, nSenseWords, nExtraWords, nPreWords};
// If there are no triggers we are done
if (!nWords) return kit;
if (!kit.m_nVecWords) return kit;
FileLine* const flp = netlistp->topScopep()->fileline();
// Creates read/write reference
const auto rd = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::READ}; };
const auto wr = [flp](AstVarScope* vp) { return new AstVarRef{flp, vp, VAccess::WRITE}; };
// Construct the comp and dump functions
@ -412,7 +529,7 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
// different copies of the trigger vector. To do so, it also needs the tag
// string at runtime, which is the second argument.
AstVarScope* const dumpTrgp
= newArgument(kit.m_dumpp, kit.m_trigDTypep, "triggers", VDirection::CONSTREF);
= newArgument(kit.m_dumpp, kit.m_trigVecDTypep, "triggers", VDirection::CONSTREF);
AstVarScope* const dumpTagp
= newArgument(kit.m_dumpp, netlistp->findStringDType(), "tag", VDirection::CONSTREF);
@ -423,32 +540,26 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
AstCStmt* const cstmtp = new AstCStmt{flp};
ifp->addThensp(cstmtp);
cstmtp->add("VL_DBG_MSGS(\" No '\" + ");
cstmtp->add(new AstVarRef{flp, dumpTagp, VAccess::READ});
cstmtp->add(rd(dumpTagp));
cstmtp->add(" + \"\' region triggers active\\n\");");
}
// Adds a debug dumping statement for this trigger
const auto addDebug = [&](uint32_t index, const string& text) {
AstVarRef* const refp = new AstVarRef{flp, dumpTrgp, VAccess::READ};
const int wrdIndex = static_cast<int>(index / WORD_SIZE);
const int bitIndex = static_cast<int>(index % WORD_SIZE);
AstNodeExpr* const aselp = new AstArraySel{flp, refp, wrdIndex};
AstNodeExpr* const aselp = new AstArraySel{flp, rd(dumpTrgp), wrdIndex};
AstNodeExpr* const condp = new AstSel{flp, aselp, bitIndex, 1};
AstIf* const ifp = new AstIf{flp, condp};
kit.m_dumpp->addStmtsp(ifp);
AstCStmt* const cstmtp = new AstCStmt{flp};
ifp->addThensp(cstmtp);
cstmtp->add("VL_DBG_MSGS(\" '\" + ");
cstmtp->add(new AstVarRef{flp, dumpTagp, VAccess::READ});
cstmtp->add(rd(dumpTagp));
cstmtp->add(" + \"' region trigger index " + std::to_string(index) + " is active: " + text
+ "\\n\");");
};
// Add a print for each of the extra triggers
for (unsigned i = 0; i < extraTriggers.size(); ++i) {
addDebug(i, "Internal '" + name + "' trigger - " + extraTriggers.m_descriptions.at(i));
}
// Add sense trigger computation
// List of trigger computation expressions
std::vector<AstNodeExpr*> trigps;
@ -464,19 +575,15 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
continue;
}
// Index of this trigger in the trigger vector
const uint32_t index = nExtraTriggers + i;
// Create the trigger computation expression
const auto& pair = senExprBuilder.build(senItemp);
trigps.emplace_back(pair.first);
// Add initialization time trigger
if (pair.second || v3Global.opt.xInitialEdge()) {
AstVarRef* const refp = new AstVarRef{flp, kit.m_vscp, VAccess::WRITE};
const int wrdIndex = static_cast<int>(index / WORD_SIZE);
const int bitIndex = static_cast<int>(index % WORD_SIZE);
AstNodeExpr* const wordp = new AstArraySel{flp, refp, wrdIndex};
const int wrdIndex = static_cast<int>(i / WORD_SIZE);
const int bitIndex = static_cast<int>(i % WORD_SIZE);
AstNodeExpr* const wordp = new AstArraySel{flp, wr(kit.m_vscp), wrdIndex};
AstNodeExpr* const lhsp = new AstSel{flp, wordp, bitIndex, 1};
AstNodeExpr* const rhsp = new AstConst{flp, AstConst::BitTrue{}};
initialTrigsp = AstNode::addNext(initialTrigsp, new AstAssign{flp, lhsp, rhsp});
@ -489,11 +596,11 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
ss << ")";
std::string desc = VString::quoteBackslash(ss.str());
desc = VString::replaceSubstr(desc, "\n", "\\n");
addDebug(index, desc);
addDebug(i, desc);
}
UASSERT(trigps.size() == nSenseTriggers, "Inconsistent number of trigger expressions");
// Assign trigger vector one word at a time
// Assign sense triggers vector one word at a time
AstNodeStmt* trigStmtsp = nullptr;
for (size_t i = 0; i < nSenseTriggers; i += WORD_SIZE) {
// Concatenate all bits in this trigger word using a balanced
@ -507,24 +614,39 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
}
// Set the whole word in the trigger vector
const uint32_t wordIndex = nExtraWords + i / WORD_SIZE;
AstVarRef* const refp = new AstVarRef{flp, kit.m_vscp, VAccess::WRITE};
AstArraySel* const aselp = new AstArraySel{flp, refp, static_cast<int>(wordIndex)};
const int wordIndex = static_cast<int>(i / WORD_SIZE);
AstArraySel* const aselp = new AstArraySel{flp, wr(kit.m_vscp), wordIndex};
trigStmtsp = AstNode::addNext(trigStmtsp, new AstAssign{flp, aselp, trigps[i]});
}
trigps.clear();
// Construct the map from old SenTrees to new SenTrees
// Add a print for each of the extra triggers
for (unsigned i = 0; i < extraTriggers.size(); ++i) {
addDebug(nSenseTriggers + i,
"Internal '" + name + "' trigger - " + extraTriggers.m_descriptions.at(i));
}
// Construct the maps from old SenTrees to new SenTrees
{
std::vector<uint32_t> indices;
indices.reserve(32);
// Map regular SenTrees to the Sense triggers
for (const AstSenTree* const senTreep : senTreeps) {
indices.clear();
for (const AstSenItem *itemp = senTreep->sensesp(), *nextp; itemp; itemp = nextp) {
nextp = VN_AS(itemp->nextp(), SenItem);
indices.push_back(senItem2TrigIdx.at(*itemp));
}
kit.m_map[senTreep] = kit.newTriggerSenTree(kit.m_vscp, indices);
kit.m_mapVec[senTreep] = kit.newTriggerSenTree(kit.m_vscp, indices);
}
// Map Pre SenTrees to the Pre triggers
for (const AstSenTree* const senTreep : preTreeps) {
indices.clear();
for (const AstSenItem *itemp = senTreep->sensesp(), *nextp; itemp; itemp = nextp) {
nextp = VN_AS(itemp->nextp(), SenItem);
indices.push_back(senItem2TrigIdx.at(*itemp) + kit.m_nVecWords * WORD_SIZE);
}
kit.m_mapPre[senTreep] = kit.newTriggerSenTree(kit.m_vscp, indices);
}
}
@ -537,6 +659,7 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
// Assemble the trigger computation function
{
AstCFunc* const fp = kit.m_compp;
AstScope* const scopep = netlistp->topScopep()->scopep();
// Profiling push
if (v3Global.opt.profExec()) fp->addStmtsp(util::profExecSectionPush(flp, "trig " + name));
// Trigger computation
@ -545,15 +668,37 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, //
for (AstNodeStmt* const nodep : senResults.m_postUpdates) fp->addStmtsp(nodep);
// Add the initialization time triggers
if (initialTrigsp) {
AstScope* const scopep = netlistp->topScopep()->scopep();
AstVarScope* const vscp = scopep->createTemp("__V" + name + "DidInit", 1);
AstVarRef* const condp = new AstVarRef{flp, vscp, VAccess::READ};
AstIf* const ifp = new AstIf{flp, new AstNot{flp, condp}};
AstIf* const ifp = new AstIf{flp, new AstNot{flp, rd(vscp)}};
fp->addStmtsp(ifp);
ifp->branchPred(VBranchPred::BP_UNLIKELY);
ifp->addThensp(util::setVar(vscp, 1));
ifp->addThensp(initialTrigsp);
}
// If there are 'pre' triggers, compute them
if (kit.m_nPreWords) {
// Add an argument to the function that takes the latched values
AstVarScope* const latchedp
= newArgument(fp, kit.m_trigVecDTypep, "latched", VDirection::CONSTREF);
// Add loop counter variable - this can't be local because we call util::splitCheck
AstVarScope* const nVscp = scopep->createTemp("__V" + name + "TrigPreLoopCounter", 32);
nVscp->varp()->noReset(true);
// Add a loop to compute the pre words
AstLoop* const loopp = new AstLoop{flp};
fp->addStmtsp(util::setVar(nVscp, 0));
fp->addStmtsp(loopp);
// Loop body
AstNodeExpr* const offsetp = new AstConst{flp, kit.m_nVecWords};
AstNodeExpr* const lIdxp = new AstAdd{flp, rd(nVscp), offsetp};
AstNodeExpr* const lhsp = new AstArraySel{flp, wr(kit.m_vscp), lIdxp};
AstNodeExpr* const aWordp = new AstArraySel{flp, rd(kit.m_vscp), rd(nVscp)};
AstNodeExpr* const bWordp = new AstArraySel{flp, rd(latchedp), rd(nVscp)};
AstNodeExpr* const rhsp = new AstAnd{flp, aWordp, new AstNot{flp, bWordp}};
AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, nPreWords};
loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
loopp->addStmtsp(util::incrementVar(nVscp));
loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}});
}
// Add a call to the dumping function if debug is enabled
fp->addStmtsp(kit.newDumpCall(kit.m_vscp, name, true));
// Profiling pop

2
test_regress/t/t_flag_csplit_groups.py
View File

@ -125,7 +125,7 @@ test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_clas
test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2")
# Check combine count
test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (220 if test.vltmt else 206))
test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (219 if test.vltmt else 205))
test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_FAST + (\d+)', 2)
test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_SLOW + (\d+)', 2)

4
test_regress/t/t_hier_block_chained.py
View File

@ -32,9 +32,9 @@ test.compile(
if test.vltmt:
test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt",
r'Optimizations, Thread schedule count\s+(\d+)', 2)
r'Optimizations, Thread schedule count\s+(\d+)', 4)
test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt",
r'Optimizations, Thread schedule total tasks\s+(\d+)', 3)
r'Optimizations, Thread schedule total tasks\s+(\d+)', 6)
test.execute()

1648
test_regress/t/t_json_only_debugcheck.out
View File

File diff suppressed because it is too large Load Diff

2
test_regress/t/t_lint_didnotconverge_bad.out
View File

@ -1,3 +1,3 @@
-V{t#,#} 'stl' region trigger index 64 is active: @([hybrid] a)
-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] a)
%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries
Aborting...

7
test_regress/t/t_scheduling_many_clocks.py
View File

@ -13,7 +13,12 @@ test.sim_time = 100000
test.scenarios('simulator')
test.compile()
test.compile(verilator_flags2=["--stats"])
if test.vlt or test.vltmt:
test.file_grep(test.stats, r"Scheduling, 'act' extra triggers\s+(\d+)", 1)
test.file_grep(test.stats, r"Scheduling, 'act' pre triggers\s+(\d+)", 1)
test.file_grep(test.stats, r"Scheduling, 'act' sense triggers\s+(\d+)", 228)
test.execute()

6
test_regress/t/t_scheduling_many_clocks.v
View File

@ -26,6 +26,7 @@ module t(/*AUTOARG*/
endfunction
int cyc = 0;
bit par = 0;
always @(posedge clk) begin
if (~|gclk) begin
gclk[0] = 1'b1;
@ -33,9 +34,12 @@ module t(/*AUTOARG*/
gclk = {gclk[N-2:0], gclk[N-1]};
end
// This make the always block requires a 'pre' trigger (and makes it non splitable)
par <= ^gclk;
cyc <= cyc + 32'd1;
if (cyc == ITERATIONS*N - 1) begin
$display("cyc");
$display("final cycle: %0d, par: %0d", cyc, par);
$write("*-* All Finished *-*\n");
$finish;
end

219
test_regress/t/t_timing_debug1.out
View File

File diff suppressed because it is too large Load Diff

70
test_regress/t/t_timing_debug2.out
View File

@ -91,7 +91,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#} Committing processes waiting for @([event] t.ec.e):
-V{t#,#} - Process waiting at t/t_timing_class.v:111
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -111,7 +110,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -139,7 +137,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -157,7 +154,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -174,7 +170,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -194,7 +189,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -226,7 +220,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -243,7 +236,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -263,7 +255,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -290,7 +281,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -308,7 +298,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -325,7 +314,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -345,7 +333,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -378,7 +365,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 0 is active: @([event] t.ec.e)
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -406,7 +392,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -433,7 +418,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -461,7 +445,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -494,7 +477,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -520,7 +502,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -545,7 +526,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -573,7 +553,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -610,7 +589,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -635,7 +613,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -663,7 +640,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -696,7 +672,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -722,7 +697,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -747,7 +721,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -775,7 +748,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -810,7 +782,6 @@
-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37
-V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting resumption
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -836,7 +807,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -859,7 +829,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -883,7 +852,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -911,7 +879,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -928,7 +895,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -945,7 +911,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -965,7 +930,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -990,7 +954,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1007,7 +970,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1027,7 +989,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1051,7 +1012,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1068,7 +1028,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1088,7 +1047,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1113,7 +1071,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1135,7 +1092,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1152,7 +1108,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1172,7 +1127,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1196,7 +1150,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1213,7 +1166,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1233,7 +1185,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1268,7 +1219,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1284,7 +1234,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1298,7 +1247,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1315,7 +1263,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1336,7 +1283,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1350,7 +1296,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1367,7 +1312,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1390,7 +1334,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1404,7 +1347,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1421,7 +1363,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1441,7 +1382,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1455,7 +1395,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1472,7 +1411,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1492,7 +1430,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1506,7 +1443,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1523,7 +1459,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1541,7 +1476,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1555,7 +1489,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1572,7 +1505,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime())
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___timing_resume
@ -1592,7 +1524,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba
@ -1606,7 +1537,6 @@
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_timing_debug2___024root___timing_commit
-V{t#,#}+ Vt_timing_debug2___024root___trigger_andNot__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act
-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act
-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba

2
test_regress/t/t_unopt_converge_initial_run_bad.out
View File

@ -1,3 +1,3 @@
-V{t#,#} 'stl' region trigger index 64 is active: @([hybrid] x)
-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x)
%Error: t/t_unopt_converge_initial.v:7: Settle region did not converge after 100 tries
Aborting...

2
test_regress/t/t_unopt_converge_print_bad.out
View File

@ -1,3 +1,3 @@
-V{t#,#} 'stl' region trigger index 64 is active: @([hybrid] x)
-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x)
%Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries
Aborting...

2
test_regress/t/t_unopt_converge_run_bad.out
View File

@ -1,3 +1,3 @@
-V{t#,#} 'stl' region trigger index 64 is active: @([hybrid] x)
-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x)
%Error: t/t_unopt_converge.v:7: Settle region did not converge after 5 tries
Aborting...

3
test_regress/t/t_verilated_debug.out
View File

@ -20,7 +20,6 @@ internalsDump:
-V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act
-V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_verilated_debug___024root___trigger_andNot__act
-V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act
-V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba
-V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act
@ -34,7 +33,6 @@ internalsDump:
-V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act
-V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act
-V{t#,#} 'act' region trigger index 0 is active: @(posedge clk)
-V{t#,#}+ Vt_verilated_debug___024root___trigger_andNot__act
-V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act
-V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba
-V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act
@ -47,7 +45,6 @@ internalsDump:
-V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act
-V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act
-V{t#,#} No 'act' region triggers active
-V{t#,#}+ Vt_verilated_debug___024root___trigger_andNot__act
-V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act
-V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba
-V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act

142
test_regress/t/t_xml_debugcheck.out
View File

@ -608,17 +608,17 @@
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="in" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="n" dtype_id="4" vartype="bit" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="4">
<var loc="a,0,0,0,0" name="n" dtype_id="18" vartype="IData" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="18">
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</assign>
<loop loc="d,11,8,11,9">
<begin>
<if loc="d,11,8,11,9">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="in" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</arraysel>
<begin>
<creturn loc="d,11,8,11,9">
@ -626,19 +626,19 @@
</creturn>
</begin>
</if>
<assign loc="a,0,0,0,0" dtype_id="4">
<add loc="a,0,0,0,0" dtype_id="4">
<assign loc="a,0,0,0,0" dtype_id="18">
<add loc="a,0,0,0,0" dtype_id="18">
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</add>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</gt>
</looptest>
</begin>
@ -1483,62 +1483,6 @@
</begin>
</if>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_trigger_andNot__act">
<var loc="a,0,0,0,0" name="out" dtype_id="5" dir="output" vartype="unknown" origName="out"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="out" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="inA" dtype_id="5" dir="const ref" vartype="unknown" origName="inA"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="inA" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="inB" dtype_id="5" dir="const ref" vartype="unknown" origName="inB"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="inB" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="n" dtype_id="4" vartype="bit" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="4">
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
</assign>
<loop loc="d,11,8,11,9">
<begin>
<assign loc="d,11,8,11,9" dtype_id="16">
<and loc="d,11,8,11,9" dtype_id="16">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="inA" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
</arraysel>
<not loc="d,11,8,11,9" dtype_id="16">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="inB" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
</arraysel>
</not>
</and>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
</arraysel>
</assign>
<assign loc="a,0,0,0,0" dtype_id="4">
<add loc="a,0,0,0,0" dtype_id="4">
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
</add>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
</gt>
</looptest>
</begin>
</loop>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_trigger_orInto__act">
<var loc="a,0,0,0,0" name="out" dtype_id="5" dir="inout" vartype="unknown" origName="out"/>
<creset loc="a,0,0,0,0">
@ -1548,10 +1492,10 @@
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="in" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="n" dtype_id="4" vartype="bit" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="4">
<var loc="a,0,0,0,0" name="n" dtype_id="18" vartype="IData" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="18">
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</assign>
<loop loc="d,11,8,11,9">
<begin>
@ -1559,50 +1503,39 @@
<or loc="d,11,8,11,9" dtype_id="16">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</arraysel>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="in" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</arraysel>
</or>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</arraysel>
</assign>
<assign loc="a,0,0,0,0" dtype_id="4">
<add loc="a,0,0,0,0" dtype_id="4">
<assign loc="a,0,0,0,0" dtype_id="18">
<add loc="a,0,0,0,0" dtype_id="18">
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</add>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</gt>
</looptest>
</begin>
</loop>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_eval_phase__act">
<var loc="d,11,8,11,9" name="__VpreTriggered" dtype_id="5" vartype="" origName="__VpreTriggered"/>
<creset loc="d,11,8,11,9">
<varref loc="d,11,8,11,9" name="__VpreTriggered" dtype_id="5"/>
</creset>
<stmtexpr loc="a,0,0,0,0">
<ccall loc="a,0,0,0,0" dtype_id="6" func="_eval_triggers__act"/>
</stmtexpr>
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_trigger_andNot__act">
<varref loc="d,11,8,11,9" name="__VpreTriggered" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
</ccall>
<ccall loc="d,11,8,11,9" dtype_id="6" func="_eval_triggers__act"/>
</stmtexpr>
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_trigger_orInto__act">
@ -1619,10 +1552,10 @@
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="out" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="n" dtype_id="4" vartype="bit" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="4">
<var loc="a,0,0,0,0" name="n" dtype_id="18" vartype="IData" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="18">
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</assign>
<loop loc="d,11,8,11,9">
<begin>
@ -1630,29 +1563,29 @@
<const loc="d,11,8,11,9" name="64&apos;h0" dtype_id="17"/>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</arraysel>
</assign>
<assign loc="a,0,0,0,0" dtype_id="4">
<add loc="a,0,0,0,0" dtype_id="4">
<assign loc="a,0,0,0,0" dtype_id="18">
<add loc="a,0,0,0,0" dtype_id="18">
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</add>
<varref loc="a,0,0,0,0" name="n" dtype_id="4"/>
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="4"/>
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
</gt>
</looptest>
</begin>
</loop>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_eval_phase__nba">
<var loc="d,11,8,11,9" name="__VnbaExecute" dtype_id="18" vartype="bit" origName="__VnbaExecute"/>
<var loc="d,11,8,11,9" name="__VnbaExecute" dtype_id="19" vartype="bit" origName="__VnbaExecute"/>
<assign loc="a,0,0,0,0" dtype_id="7">
<ccall loc="d,11,8,11,9" dtype_id="7" func="_trigger_anySet__act">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
@ -1765,7 +1698,7 @@
<if loc="d,15,10,15,13">
<and loc="d,15,10,15,13" dtype_id="1">
<varref loc="d,15,10,15,13" name="clk" dtype_id="1"/>
<const loc="d,15,10,15,13" name="8&apos;hfe" dtype_id="19"/>
<const loc="d,15,10,15,13" name="8&apos;hfe" dtype_id="20"/>
</and>
<begin>
<cstmt loc="d,15,10,15,13">
@ -1864,7 +1797,7 @@
<basicdtype loc="d,33,24,33,27" id="1" name="logic"/>
<basicdtype loc="d,53,16,53,17" id="13" name="logic" left="31" right="0"/>
<basicdtype loc="d,17,17,17,18" id="2" name="logic" left="3" right="0"/>
<enumdtype loc="d,17,12,17,16" id="20" name="t.my_t" sub_dtype_id="2">
<enumdtype loc="d,17,12,17,16" id="21" name="t.my_t" sub_dtype_id="2">
<enumitem loc="d,18,24,18,27" name="E01" dtype_id="10">
<const loc="d,18,30,18,31" name="4&apos;h1" dtype_id="10"/>
</enumitem>
@ -1876,7 +1809,7 @@
</enumitem>
</enumdtype>
<basicdtype loc="d,23,4,23,11" id="3" name="integer" left="31" right="0" signed="true"/>
<refdtype loc="d,24,4,24,8" id="21" name="my_t" sub_dtype_id="2"/>
<refdtype loc="d,24,4,24,8" id="22" name="my_t" sub_dtype_id="2"/>
<basicdtype loc="d,28,4,28,10" id="9" name="string"/>
<unpackarraydtype loc="d,17,12,17,16" id="11" sub_dtype_id="2">
<range loc="d,17,12,17,16">
@ -1905,13 +1838,14 @@
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
</range>
</unpackarraydtype>
<basicdtype loc="a,0,0,0,0" id="4" name="bit" left="31" right="0"/>
<basicdtype loc="a,0,0,0,0" id="18" name="IData" left="31" right="0"/>
<basicdtype loc="d,63,14,63,21" id="17" name="logic" left="63" right="0"/>
<basicdtype loc="d,11,8,11,9" id="18" name="bit"/>
<basicdtype loc="d,11,8,11,9" id="19" name="bit"/>
<basicdtype loc="d,11,8,11,9" id="4" name="bit" left="31" right="0"/>
<basicdtype loc="d,63,22,63,25" id="7" name="logic" left="31" right="0"/>
<basicdtype loc="d,32,11,32,14" id="10" name="logic" left="31" right="0"/>
<basicdtype loc="d,38,15,38,16" id="12" name="logic" left="31" right="0"/>
<basicdtype loc="d,15,10,15,13" id="19" name="logic" left="7" right="0"/>
<basicdtype loc="d,15,10,15,13" id="20" name="logic" left="7" right="0"/>
</typetable>
<constpool>
<module loc="a,0,0,0,0" name="@CONST-POOL@" origName="@CONST-POOL@">