Fix ITOD internal error on real conversions, bug491.

Changes

@@ -19,6 +19,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Fix generate operators not short circuiting, bug413.  [by Jeremy Bennett]
 
+****  Fix ITOD internal error on real conversions, bug491.  [Alex Solomatnikov]
+
 ****  Fix imports causing symbol table error, bug490.  [Alex Solomatnikov]
 
 * Verilator 3.833 2012/04/15

src/V3Width.cpp

@@ -1929,6 +1929,7 @@ private:
 	AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
 	AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
 	AstNodeBiop* newp = NULL;
+	// No width change on output;...		// All below have bool or double outputs
 	switch (nodep->type()) {
 	case AstType::atADD:  				newp = new AstAddD	(fl,lhsp,rhsp); break;
 	case AstType::atSUB:  				newp = new AstSubD	(fl,lhsp,rhsp); break;
@@ -1946,7 +1947,7 @@ private:
 	}
 	UINFO(6,"   ReplaceWithDVersion: "<<nodep<<" w/ "<<newp<<endl);
 	nodep->replaceWith(newp);
-	newp->widthSignedFrom(nodep);
+	// No width change; the default created type (bool or double) is correct
 	pushDeletep(nodep); nodep=NULL;
 	return newp;
     }

test_regress/t/t_func_real_abs.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_func_real_abs.v

@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+//bug591
+
+module t (/*AUTOARG*/);
+
+   function real ABS (real num);
+      ABS = (num < 0) ? -num : num;
+   endfunction
+
+   function logic range_chk;
+      input real last;
+      input real period;
+      input real cmp;
+      range_chk = 0;
+      if ( last >= 0 ) begin
+         if ( ABS(last - period) > cmp ) begin
+	    range_chk = 1;
+         end
+      end
+   endfunction
+
+   initial begin
+      if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop;
+      if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop;
+      if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop;
+      if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop;
+      if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule