Reject automatic sequence event arguments per IEEE 9.4.2.4 and apply test review feedback

This commit is contained in:
Yilou Wang 2026-07-04 10:49:13 +02:00
parent 951404eac7
commit 2d88c088ce
4 changed files with 14 additions and 14 deletions

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@ -116,13 +116,12 @@ class SeqEventLowerVisitor final : public VNVisitor {
v3Global.setHasEvents(); v3Global.setHasEvents();
funcrefp->unlinkFrBack(); funcrefp->unlinkFrBack();
nodep->sensp(new AstVarRef{flp, eventp, VAccess::READ}); nodep->sensp(new AstVarRef{flp, eventp, VAccess::READ});
// An automatic actual cannot be referenced from the module-level cover
const bool automaticActual = funcrefp->exists([](const AstNodeVarRef* refp) { const bool automaticActual = funcrefp->exists([](const AstNodeVarRef* refp) {
return refp->varp() && refp->varp()->lifetime().isAutomatic(); return refp->varp() && refp->varp()->lifetime().isAutomatic();
}); });
if (automaticActual) { if (automaticActual) {
nodep->v3warn(E_UNSUPPORTED, "Unsupported: automatic variable as an argument" nodep->v3error("Arguments to a sequence used as an event control must be"
" of a sequence used as an event control"); " static (IEEE 1800-2023 9.4.2.4)");
VN_AS(funcrefp->taskp(), Sequence)->isReferenced(false); VN_AS(funcrefp->taskp(), Sequence)->isReferenced(false);
VL_DO_DANGLING(pushDeletep(funcrefp), funcrefp); VL_DO_DANGLING(pushDeletep(funcrefp), funcrefp);
return; return;

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@ -15,9 +15,9 @@ module t (
int unsigned crc = 32'h1; int unsigned crc = 32'h1;
bit a, b, c; bit a, b, c;
bit a1, a2, a3, b1; bit a1, a2, a3, b1;
int cyc = 0; int cyc;
int seq_hits = 0, seq_hits2 = 0, ref_hits = 0, one_hits = 0, dc_hits = 0; int seq_hits, seq_hits2, ref_hits, one_hits, dc_hits;
int rng_hits = 0, rng_ref = 0; int rng_hits, rng_ref;
// verilog_format: off // verible does not support clocking events inside sequence declarations // verilog_format: off // verible does not support clocking events inside sequence declarations
sequence seq; sequence seq;

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@ -1,12 +1,13 @@
%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:25:7: Unsupported: automatic variable as an argument of a sequence used as an event control %Error: t/t_assert_seq_event_unsup.v:25:7: Arguments to a sequence used as an event control must be static (IEEE 1800-2023 9.4.2.4)
: ... note: In instance 't' : ... note: In instance 't'
25 | @(s_arg(x)); 25 | @(s_arg(x));
| ^~~~~ | ^~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:15:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk) %Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:15:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk)
: ... note: In instance 't' : ... note: In instance 't'
15 | @(g) a ##1 b; 15 | @(g) a ##1 b;
| ^ | ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:29:6: Unsupported: Unclocked assertion %Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:29:6: Unsupported: Unclocked assertion
: ... note: In instance 't' : ... note: In instance 't'
29 | @s_nonedge; 29 | @s_nonedge;

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@ -10,10 +10,10 @@ module t;
1; 1;
endsequence endsequence
// s_one is referenced only from another sequence that is never expanded into initial begin
// an assertion, so it is left referenced outside any assertion property. @s_one;
sequence s_two; $display("got sequence");
s_one ##1 1; $finish;
endsequence end
endmodule endmodule