Reject automatic sequence event arguments per IEEE 9.4.2.4 and apply test review feedback
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@ -116,13 +116,12 @@ class SeqEventLowerVisitor final : public VNVisitor {
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v3Global.setHasEvents();
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v3Global.setHasEvents();
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funcrefp->unlinkFrBack();
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funcrefp->unlinkFrBack();
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nodep->sensp(new AstVarRef{flp, eventp, VAccess::READ});
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nodep->sensp(new AstVarRef{flp, eventp, VAccess::READ});
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// An automatic actual cannot be referenced from the module-level cover
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const bool automaticActual = funcrefp->exists([](const AstNodeVarRef* refp) {
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const bool automaticActual = funcrefp->exists([](const AstNodeVarRef* refp) {
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return refp->varp() && refp->varp()->lifetime().isAutomatic();
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return refp->varp() && refp->varp()->lifetime().isAutomatic();
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});
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});
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if (automaticActual) {
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if (automaticActual) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: automatic variable as an argument"
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nodep->v3error("Arguments to a sequence used as an event control must be"
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" of a sequence used as an event control");
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" static (IEEE 1800-2023 9.4.2.4)");
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VN_AS(funcrefp->taskp(), Sequence)->isReferenced(false);
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VN_AS(funcrefp->taskp(), Sequence)->isReferenced(false);
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VL_DO_DANGLING(pushDeletep(funcrefp), funcrefp);
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VL_DO_DANGLING(pushDeletep(funcrefp), funcrefp);
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return;
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return;
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@ -15,9 +15,9 @@ module t (
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int unsigned crc = 32'h1;
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int unsigned crc = 32'h1;
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bit a, b, c;
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bit a, b, c;
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bit a1, a2, a3, b1;
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bit a1, a2, a3, b1;
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int cyc = 0;
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int cyc;
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int seq_hits = 0, seq_hits2 = 0, ref_hits = 0, one_hits = 0, dc_hits = 0;
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int seq_hits, seq_hits2, ref_hits, one_hits, dc_hits;
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int rng_hits = 0, rng_ref = 0;
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int rng_hits, rng_ref;
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// verilog_format: off // verible does not support clocking events inside sequence declarations
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// verilog_format: off // verible does not support clocking events inside sequence declarations
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sequence seq;
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sequence seq;
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@ -1,12 +1,13 @@
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%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:25:7: Unsupported: automatic variable as an argument of a sequence used as an event control
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%Error: t/t_assert_seq_event_unsup.v:25:7: Arguments to a sequence used as an event control must be static (IEEE 1800-2023 9.4.2.4)
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: ... note: In instance 't'
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: ... note: In instance 't'
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25 | @(s_arg(x));
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25 | @(s_arg(x));
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| ^~~~~
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| ^~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:15:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk)
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%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:15:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk)
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: ... note: In instance 't'
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: ... note: In instance 't'
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15 | @(g) a ##1 b;
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15 | @(g) a ##1 b;
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| ^
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| ^
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:29:6: Unsupported: Unclocked assertion
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%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:29:6: Unsupported: Unclocked assertion
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: ... note: In instance 't'
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: ... note: In instance 't'
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29 | @s_nonedge;
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29 | @s_nonedge;
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@ -10,10 +10,10 @@ module t;
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1;
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1;
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endsequence
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endsequence
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// s_one is referenced only from another sequence that is never expanded into
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initial begin
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// an assertion, so it is left referenced outside any assertion property.
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@s_one;
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sequence s_two;
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$display("got sequence");
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s_one ##1 1;
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$finish;
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endsequence
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end
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endmodule
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endmodule
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