Optimize functions inlined from packages in Dfg (#7091)
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@ -274,6 +274,8 @@ private:
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UASSERT_OBJ(
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UASSERT_OBJ(
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!(v3Global.assertScoped() && m_inScope && nodep->varp() && !nodep->varScopep()), nodep,
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!(v3Global.assertScoped() && m_inScope && nodep->varp() && !nodep->varScopep()), nodep,
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"VarRef missing VarScope pointer");
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"VarRef missing VarScope pointer");
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UASSERT_OBJ(!v3Global.assertScoped() || !nodep->classOrPackagep(), nodep,
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"VarRef classOrPackagep must be nullptr after V3Scope");
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if (m_cfuncp) {
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if (m_cfuncp) {
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// Check if variable is an in-scope local, otherwise mark as suspect
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// Check if variable is an in-scope local, otherwise mark as suspect
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if (const AstVar* const varp = nodep->varp()) {
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if (const AstVar* const varp = nodep->varp()) {
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@ -73,6 +73,7 @@ class ScopeVisitor final : public VNVisitor {
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"Can't locate class or package scope");
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"Can't locate class or package scope");
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scopep = it2->second;
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scopep = it2->second;
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}
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}
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nodep->classOrPackagep(nullptr); // No longer needed after V3Scope
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// Search up the scope hierarchy for the variable
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// Search up the scope hierarchy for the variable
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AstVarScope* varscp = nullptr;
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AstVarScope* varscp = nullptr;
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AstScope* searchScopep = scopep;
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AstScope* searchScopep = scopep;
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@ -6,6 +6,12 @@
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`define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr
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`define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr
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package pkg;
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function automatic logic [7:0] sub(input logic [7:0] a, input logic [7:0] b);
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return a - b;
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endfunction
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endpackage
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module t (
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module t (
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`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py
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`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py
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rand_a, rand_b, srand_a, srand_b
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rand_a, rand_b, srand_a, srand_b
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@ -524,4 +530,19 @@ module t (
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end
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end
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`signal(USES_LOOP_VAR, uses_loop_var);
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`signal(USES_LOOP_VAR, uses_loop_var);
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function automatic logic [7:0] add(input logic [7:0] a, input logic [7:0] b);
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return a + b;
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endfunction
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logic [7:0] func_1;
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always_comb begin
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func_1 = add(rand_a[7:0], rand_b[7:0]);
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end
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`signal(FUNC_1, func_1);
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logic [7:0] func_2;
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always_comb begin
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func_2 = pkg::sub(rand_a[7:0], rand_b[7:0]);
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end
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`signal(FUNC_2, func_2);
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endmodule
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endmodule
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