Optimize mask/and above conditionals.

Changes

@@ -28,7 +28,7 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Support quoted arguments in -f files, bug1535. [Yves Mathieu]
 
-****  Optimize modulus by power-of-two constants.
+****  Optimize modulus by power-of-two constants, and masked conditionals.
 
 ****  Fix detecting missing reg types, bug1570. [Jacko Dirks]
 

src/V3Const.cpp

@@ -218,6 +218,31 @@ private:
         else nodep->rhsp(cp);
         return true;
     }
+    bool matchAndCond(AstAnd* nodep) {
+        // Push down a AND into conditional, when one side of conditional is constant
+        // (otherwise we'd be trading one operation for two operations)
+        // V3Clean often makes this pattern, as it postpones the AND until
+        // as high as possible, which is usally the right choice, except for this.
+        AstNodeCond* condp = VN_CAST(nodep->rhsp(), NodeCond);
+        if (!condp) return false;
+        if (!VN_IS(condp->expr1p(), Const) && !VN_IS(condp->expr2p(), Const)) return false;
+        AstConst* maskp = VN_CAST(nodep->lhsp(), Const);
+        if (!maskp) return false;
+        UINFO(4, "AND(CONSTm, CONDcond(c, i, e))->CONDcond(c, AND(m,i), AND(m, e)) "<<nodep<<endl);
+        AstNodeCond* newp = (AstNodeCond*)condp->cloneType
+            (condp->condp()->unlinkFrBack(),
+             new AstAnd(nodep->fileline(),
+                        maskp->cloneTree(false),
+                        condp->expr1p()->unlinkFrBack()),
+             new AstAnd(nodep->fileline(),
+                        maskp->cloneTree(false),
+                        condp->expr2p()->unlinkFrBack()));
+        newp->dtypeFrom(nodep);
+        newp->expr1p()->dtypeFrom(nodep);  // As And might have been to change widths
+        newp->expr2p()->dtypeFrom(nodep);
+        nodep->replaceWith(newp); nodep->deleteTree(); VL_DANGLING(nodep);
+        return true;
+    }
     static bool operandShiftSame(const AstNode* nodep) {
         const AstNodeBiop* np = VN_CAST_CONST(nodep, NodeBiop);
         {
@@ -2442,6 +2467,7 @@ private:
     TREEOPV("AstConcat{$lhsp.castSel, $rhsp.castSel, ifAdjacentSel(VN_CAST($lhsp,,Sel),,VN_CAST($rhsp,,Sel))}",  "replaceConcatSel(nodep)");
     TREEOPV("AstConcat{ifConcatMergeableBiop($lhsp), concatMergeable($lhsp,,$rhsp)}", "replaceConcatMerge(nodep)");
     // Common two-level operations that can be simplified
+    TREEOP ("AstAnd {$lhsp.castConst,matchAndCond(nodep)}",           "DONE");
     TREEOP ("AstAnd {$lhsp.castOr, $rhsp.castOr, operandAndOrSame(nodep)}",     "replaceAndOr(nodep)");
     TREEOP ("AstOr  {$lhsp.castAnd,$rhsp.castAnd,operandAndOrSame(nodep)}",     "replaceAndOr(nodep)");
     TREEOP ("AstOr  {matchOrAndNot(nodep)}",            "DONE");

test_regress/t/t_math_cond_clean.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_cond_clean.v

@@ -0,0 +1,94 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer      cyc=0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [3:0]  cnt = crc[3:0];
+   wire [6:0]  decr = crc[14:8];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [3:0]           next;                   // From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+              // Outputs
+              .next                     (next[3:0]),
+              // Inputs
+              .cnt                      (cnt[3:0]),
+              .decr                     (decr[6:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {60'h0, next};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+      end
+      else if (cyc<10) begin
+         sum <= '0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h7cd85c944415d2ef
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   next,
+   // Inputs
+   cnt, decr
+   );
+
+   input [3:0] cnt;
+   input signed [6:0] decr;
+   output reg [3:0]         next;
+
+   always_comb begin
+      reg signed [6:0] tmp;
+      tmp = 0;
+      // verilator lint_off WIDTH
+      tmp = ($signed({1'b0, cnt}) - decr);
+      // verilator lint_on WIDTH
+      if ((tmp > 15)) begin
+         next = 15;
+      end
+      else if ((tmp < 0)) begin
+         next = 0;
+      end
+      else begin
+         next = tmp[3:0];
+      end
+   end
+
+endmodule